From owner-cvs-all Tue Jun 13 2:10:41 2000 Delivered-To: cvs-all@freebsd.org Received: from freefall.freebsd.org (freefall.FreeBSD.ORG [204.216.27.21]) by hub.freebsd.org (Postfix) with ESMTP id 2950737B55F; Tue, 13 Jun 2000 02:10:38 -0700 (PDT) (envelope-from kato@FreeBSD.org) Received: (from kato@localhost) by freefall.freebsd.org (8.9.3/8.9.2) id CAA17156; Tue, 13 Jun 2000 02:10:37 -0700 (PDT) (envelope-from kato@FreeBSD.org) Message-Id: <200006130910.CAA17156@freefall.freebsd.org> From: KATO Takenori Date: Tue, 13 Jun 2000 02:10:37 -0700 (PDT) To: cvs-committers@FreeBSD.org, cvs-all@FreeBSD.org Subject: cvs commit: src/sys/conf options.i386 options.pc98 src/sys/i386/conf LINT src/sys/i386/i386 initcpu.c Sender: owner-cvs-all@FreeBSD.ORG Precedence: bulk X-Loop: FreeBSD.ORG kato 2000/06/13 02:10:37 PDT Modified files: sys/conf options.i386 options.pc98 sys/i386/conf LINT sys/i386/i386 initcpu.c Log: Added new options CPU_PPRO2CELERON and CPU_L2_LATENCY to support Socket 8 to 370 converters. When (1) CPU_PPRO2CELERON option is defined, (2) Intel CPU is found and (3) CPU ID is 0x66?, L2 cache is enabled through MSR 0x11e. The L2 cache latency value can be specified by CPU_L2_LATENCY option. Default value of L2 cache latency is 5. These options are useful if you use Socket 8 to Socket 370 converter (e.g. Power Leap's PL-Pro/II.) Most PentiumPro BIOSs don't enable L2 cache of Mendocino Celeron CPUs because they don't know Celeron CPUs. These options are needles if you use a Coppermine (FCPGA) Celeron or PentiumIII, becuase the L2 cache enable bit is hard wired and L2 cache is always enabled. Revision Changes Path 1.138 +3 -1 src/sys/conf/options.i386 1.109 +3 -1 src/sys/conf/options.pc98 1.782 +11 -1 src/sys/i386/conf/LINT 1.20 +53 -4 src/sys/i386/i386/initcpu.c To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe cvs-all" in the body of the message