From owner-svn-src-head@FreeBSD.ORG Tue Jan 4 19:32:04 2011 Return-Path: Delivered-To: svn-src-head@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 72801106564A; Tue, 4 Jan 2011 19:32:04 +0000 (UTC) (envelope-from jmallett@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id 29A428FC08; Tue, 4 Jan 2011 19:32:04 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.3/8.14.3) with ESMTP id p04JW4P4052195; Tue, 4 Jan 2011 19:32:04 GMT (envelope-from jmallett@svn.freebsd.org) Received: (from jmallett@localhost) by svn.freebsd.org (8.14.3/8.14.3/Submit) id p04JW4TC052193; Tue, 4 Jan 2011 19:32:04 GMT (envelope-from jmallett@svn.freebsd.org) Message-Id: <201101041932.p04JW4TC052193@svn.freebsd.org> From: Juli Mallett Date: Tue, 4 Jan 2011 19:32:04 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r216972 - head/sys/mips/include X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 04 Jan 2011 19:32:04 -0000 Author: jmallett Date: Tue Jan 4 19:32:03 2011 New Revision: 216972 URL: http://svn.freebsd.org/changeset/base/216972 Log: Correct an 8-year-old typo which reliably leads to typo after typo today: The macros here for generating coprocessor 0 accessors are named like: MIPS_RDRW32_COP0 That macro would produce mips_rd_() and mips_wr_() inlines to access the specified register by name from C. The problem is that the R and the W were swapped in the macros originally; it was meant to be named RDWR because it generated mips_rd_* and mips_wr_* functions, but was instead spelled RDRW, which nobody should be expected to get right by anything other than copy and paste. It's too many consonants in a row to keep straight anyway, so just prefer e.g.: MIPS_RW32_COP0 While here, add a missing #undef. Modified: head/sys/mips/include/cpufunc.h Modified: head/sys/mips/include/cpufunc.h ============================================================================== --- head/sys/mips/include/cpufunc.h Tue Jan 4 19:26:11 2011 (r216971) +++ head/sys/mips/include/cpufunc.h Tue Jan 4 19:32:03 2011 (r216972) @@ -114,7 +114,7 @@ mips_write_membar(void) * ABI checks. */ #if defined(__mips_n32) || defined(__mips_n64) -#define MIPS_RDRW64_COP0(n,r) \ +#define MIPS_RW64_COP0(n,r) \ static __inline uint64_t \ mips_rd_ ## n (void) \ { \ @@ -137,18 +137,18 @@ mips_wr_ ## n (uint64_t a0) \ } struct __hack #if defined(__mips_n64) -MIPS_RDRW64_COP0(excpc, MIPS_COP_0_EXC_PC); -MIPS_RDRW64_COP0(entrylo0, MIPS_COP_0_TLB_LO0); -MIPS_RDRW64_COP0(entrylo1, MIPS_COP_0_TLB_LO1); -MIPS_RDRW64_COP0(entryhi, MIPS_COP_0_TLB_HI); -MIPS_RDRW64_COP0(pagemask, MIPS_COP_0_TLB_PG_MASK); +MIPS_RW64_COP0(excpc, MIPS_COP_0_EXC_PC); +MIPS_RW64_COP0(entrylo0, MIPS_COP_0_TLB_LO0); +MIPS_RW64_COP0(entrylo1, MIPS_COP_0_TLB_LO1); +MIPS_RW64_COP0(entryhi, MIPS_COP_0_TLB_HI); +MIPS_RW64_COP0(pagemask, MIPS_COP_0_TLB_PG_MASK); #endif -MIPS_RDRW64_COP0(xcontext, MIPS_COP_0_TLB_XCONTEXT); +MIPS_RW64_COP0(xcontext, MIPS_COP_0_TLB_XCONTEXT); -#undef MIPS_RDRW64_COP0 +#undef MIPS_RW64_COP0 #endif -#define MIPS_RDRW32_COP0(n,r) \ +#define MIPS_RW32_COP0(n,r) \ static __inline uint32_t \ mips_rd_ ## n (void) \ { \ @@ -170,7 +170,7 @@ mips_wr_ ## n (uint32_t a0) \ mips_barrier(); \ } struct __hack -#define MIPS_RDRW32_COP0_SEL(n,r,s) \ +#define MIPS_RW32_COP0_SEL(n,r,s) \ static __inline uint32_t \ mips_rd_ ## n(void) \ { \ @@ -205,45 +205,46 @@ static __inline void mips_sync_icache (v } #endif -MIPS_RDRW32_COP0(compare, MIPS_COP_0_COMPARE); -MIPS_RDRW32_COP0(config, MIPS_COP_0_CONFIG); -MIPS_RDRW32_COP0_SEL(config1, MIPS_COP_0_CONFIG, 1); -MIPS_RDRW32_COP0_SEL(config2, MIPS_COP_0_CONFIG, 2); -MIPS_RDRW32_COP0_SEL(config3, MIPS_COP_0_CONFIG, 3); -MIPS_RDRW32_COP0(count, MIPS_COP_0_COUNT); -MIPS_RDRW32_COP0(index, MIPS_COP_0_TLB_INDEX); -MIPS_RDRW32_COP0(wired, MIPS_COP_0_TLB_WIRED); -MIPS_RDRW32_COP0(cause, MIPS_COP_0_CAUSE); +MIPS_RW32_COP0(compare, MIPS_COP_0_COMPARE); +MIPS_RW32_COP0(config, MIPS_COP_0_CONFIG); +MIPS_RW32_COP0_SEL(config1, MIPS_COP_0_CONFIG, 1); +MIPS_RW32_COP0_SEL(config2, MIPS_COP_0_CONFIG, 2); +MIPS_RW32_COP0_SEL(config3, MIPS_COP_0_CONFIG, 3); +MIPS_RW32_COP0(count, MIPS_COP_0_COUNT); +MIPS_RW32_COP0(index, MIPS_COP_0_TLB_INDEX); +MIPS_RW32_COP0(wired, MIPS_COP_0_TLB_WIRED); +MIPS_RW32_COP0(cause, MIPS_COP_0_CAUSE); #if !defined(__mips_n64) -MIPS_RDWR32_COP0(excpc, MIPS_COP_0_EXC_PC); +MIPS_RW32_COP0(excpc, MIPS_COP_0_EXC_PC); #endif -MIPS_RDRW32_COP0(status, MIPS_COP_0_STATUS); +MIPS_RW32_COP0(status, MIPS_COP_0_STATUS); /* XXX: Some of these registers are specific to MIPS32. */ #if !defined(__mips_n64) -MIPS_RDRW32_COP0(entrylo0, MIPS_COP_0_TLB_LO0); -MIPS_RDRW32_COP0(entrylo1, MIPS_COP_0_TLB_LO1); -MIPS_RDRW32_COP0(entryhi, MIPS_COP_0_TLB_HI); -MIPS_RDRW32_COP0(pagemask, MIPS_COP_0_TLB_PG_MASK); +MIPS_RW32_COP0(entrylo0, MIPS_COP_0_TLB_LO0); +MIPS_RW32_COP0(entrylo1, MIPS_COP_0_TLB_LO1); +MIPS_RW32_COP0(entryhi, MIPS_COP_0_TLB_HI); +MIPS_RW32_COP0(pagemask, MIPS_COP_0_TLB_PG_MASK); #endif -MIPS_RDRW32_COP0(prid, MIPS_COP_0_PRID); +MIPS_RW32_COP0(prid, MIPS_COP_0_PRID); /* XXX 64-bit? */ -MIPS_RDRW32_COP0_SEL(ebase, MIPS_COP_0_PRID, 1); -MIPS_RDRW32_COP0(watchlo, MIPS_COP_0_WATCH_LO); -MIPS_RDRW32_COP0_SEL(watchlo1, MIPS_COP_0_WATCH_LO, 1); -MIPS_RDRW32_COP0_SEL(watchlo2, MIPS_COP_0_WATCH_LO, 2); -MIPS_RDRW32_COP0_SEL(watchlo3, MIPS_COP_0_WATCH_LO, 3); -MIPS_RDRW32_COP0(watchhi, MIPS_COP_0_WATCH_HI); -MIPS_RDRW32_COP0_SEL(watchhi1, MIPS_COP_0_WATCH_HI, 1); -MIPS_RDRW32_COP0_SEL(watchhi2, MIPS_COP_0_WATCH_HI, 2); -MIPS_RDRW32_COP0_SEL(watchhi3, MIPS_COP_0_WATCH_HI, 3); - -MIPS_RDRW32_COP0_SEL(perfcnt0, MIPS_COP_0_PERFCNT, 0); -MIPS_RDRW32_COP0_SEL(perfcnt1, MIPS_COP_0_PERFCNT, 1); -MIPS_RDRW32_COP0_SEL(perfcnt2, MIPS_COP_0_PERFCNT, 2); -MIPS_RDRW32_COP0_SEL(perfcnt3, MIPS_COP_0_PERFCNT, 3); +MIPS_RW32_COP0_SEL(ebase, MIPS_COP_0_PRID, 1); +MIPS_RW32_COP0(watchlo, MIPS_COP_0_WATCH_LO); +MIPS_RW32_COP0_SEL(watchlo1, MIPS_COP_0_WATCH_LO, 1); +MIPS_RW32_COP0_SEL(watchlo2, MIPS_COP_0_WATCH_LO, 2); +MIPS_RW32_COP0_SEL(watchlo3, MIPS_COP_0_WATCH_LO, 3); +MIPS_RW32_COP0(watchhi, MIPS_COP_0_WATCH_HI); +MIPS_RW32_COP0_SEL(watchhi1, MIPS_COP_0_WATCH_HI, 1); +MIPS_RW32_COP0_SEL(watchhi2, MIPS_COP_0_WATCH_HI, 2); +MIPS_RW32_COP0_SEL(watchhi3, MIPS_COP_0_WATCH_HI, 3); + +MIPS_RW32_COP0_SEL(perfcnt0, MIPS_COP_0_PERFCNT, 0); +MIPS_RW32_COP0_SEL(perfcnt1, MIPS_COP_0_PERFCNT, 1); +MIPS_RW32_COP0_SEL(perfcnt2, MIPS_COP_0_PERFCNT, 2); +MIPS_RW32_COP0_SEL(perfcnt3, MIPS_COP_0_PERFCNT, 3); -#undef MIPS_RDRW32_COP0 +#undef MIPS_RW32_COP0 +#undef MIPS_RW32_COP0_SEL static __inline register_t intr_disable(void)