Date: Wed, 17 Sep 1997 12:56:40 -0700 From: Wayne Scott <wscott@ichips.intel.com> To: dg@root.com Cc: Simon Shapiro <Shimon@i-connect.net>, Terry Lambert <tlambert@primenet.com>, missmanp@milo.cfw.com, freebsd-smp@freebsd.org Subject: Re: SMP in FreeBSD 3.x.x Message-ID: <199709171956.MAA05986@pdxlx008.jf.intel.com> In-Reply-To: Your message of "Sun, 14 Sep 1997 20:55:03 PDT." <199709150355.UAA24481@implode.root.com>
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> This contradicts a paper that was given at a recent Usenix-sponsored
> conference that shows that the amount of main memory traffic in P6 systems
> is *dramatically* reduced over Pentium systems. I forget the exact ratio,
> but it is something like 1/5th. This is entirely due to the superior cache
> architecture of the P6.
For the huge application/poor hit rate case you have to remember that
Pentium does not have a write allocate cache.
So a write that misses the cache on a Pentium just writes straight to
memory. On a Pentium Pro that line is allocated in the L2 possibly
evicting another line to make room. This is more traffic if you will
never use the data again. (Rare but it does happen with some
applications like TPCC)
Dr. Nicely's prime number program (of Pentium FDIV fame) thrashes the
Pentium Pro's caches nicely this this regard.
Note write allocate is a big win for most programs.
Wayne Scott MD6 Architecture
wscott@ichips.intel.com Work #: (503) 264-4165
Disclaimer: All views expressed are my own opinions, and not necessarily
those of Intel Corporation.
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