From owner-freebsd-isdn Mon Dec 14 03:07:36 1998 Return-Path: Received: (from majordom@localhost) by hub.freebsd.org (8.8.8/8.8.8) id DAA10489 for freebsd-isdn-outgoing; Mon, 14 Dec 1998 03:07:36 -0800 (PST) (envelope-from owner-freebsd-isdn@FreeBSD.ORG) Received: from mail.rwth-aachen.de (mail.RWTH-Aachen.DE [137.226.144.9]) by hub.freebsd.org (8.8.8/8.8.8) with ESMTP id DAA10483 for ; Mon, 14 Dec 1998 03:07:30 -0800 (PST) (envelope-from heinig@hdz-ima.rwth-aachen.de) Received: from HDZ-IMA.RWTH-Aachen.de (majestix.hdz-ima.RWTH-Aachen.DE) by mail.rwth-aachen.de (PMDF V5.1-11 #30440) with ESMTP id <01J5BJ4MUUPQ00002T@mail.rwth-aachen.de> for freebsd-isdn@freebsd.org; Mon, 14 Dec 1998 07:34:23 +0100 Received: from MAJESTIX/MAIL by HDZ-IMA.RWTH-Aachen.de (Mercury 1.20); Mon, 14 Dec 1998 07:38:11 +0000 Received: from MAIL by MAJESTIX (Mercury 1.20); Sun, 13 Dec 1998 18:23:29 +0000 Received: from hdz-ima.rwth-aachen.de by HDZ-IMA.RWTH-Aachen.de (Mercury 1.20) with ESMTP; Sun, 13 Dec 1998 18:23:22 +0000 Date: Sun, 13 Dec 1998 18:21:32 +0100 From: Gerald Heinig Subject: ISAC & HSCX questions To: freebsd-isdn@FreeBSD.ORG Message-id: <3673F79C.DC25867@hdz-ima.rwth-aachen.de> Organization: Informatik im Maschinenbau / Hochschuldidaktisches Zentrum, RWTH Aachen MIME-version: 1.0 X-Mailer: Mozilla 4.5 [en] (X11; I; FreeBSD 2.2.7-RELEASE i386) Content-type: text/plain; charset=us-ascii Content-transfer-encoding: 7bit X-Accept-Language: en Sender: owner-freebsd-isdn@FreeBSD.ORG Precedence: bulk X-Loop: FreeBSD.org Hi all, I've been wading through the i4b source code lately and have got myself the docs for the ISAC and HSCX chips from Siemens. There are a few questions I wanted to ask: Why do they refer to the data read and write registers as FIFOs? There doesn't seem to be anything queue-like about them. Why isn't there any documentation about the HSCX specifically? I downloaded the HSCX docs from Siemens, but there they talk about upgrading the ISAC-S TE to a larger FIFO and other stuff. Not a whisper about how the HSCX works. The ISAC docs, however, make lots of references to it. I know these two chips are designed for each other, but why doesn't there seem to be any HSCX-specific docs? How do you find out things like a Fritz! card having 0x05 in the low order bits of (I forget) and an AVM A1 having 0x04 or 0x05 in the same place? That's card-specific, isn't it? ie. nothing to do with ISAC/HSCX... Why do the registers at offset 0x30 to 0x3b have different names than those in the Siemens docs? (Just curious) Does the Fritz! driver use the IOM functionality? (I suppose the answer to that is RTFM :-) but since I'm writing the mail now, I might as well ask...) Thanks very much for any replies Gerald -- "A man's got to know his limitations..." 'Dirty' Harry Callaghan A.K.A Clint Eastwood To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe freebsd-isdn" in the body of the message