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Date:      Sat, 14 Aug 1999 10:07:45 -0700 (PDT)
From:      "Rodney W. Grimes" <rgrimes@gndrsh.aac.dev.com>
To:        wilko@yedi.iaf.nl (Wilko Bulte)
Cc:        mike@smith.net.au, freebsd-stable@FreeBSD.ORG
Subject:   Re: On freezes in 3.2-Stable (fwd)
Message-ID:  <199908141707.KAA05443@gndrsh.aac.dev.com>
In-Reply-To: <199908140907.LAA53789@yedi.iaf.nl> from Wilko Bulte at "Aug 14, 1999 11:07:00 am"

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> As Rodney W. Grimes wrote ...
> 
> > > Er.  The Intel AD450NX has 32 DIMM sockets.  Unless someone starts 
> > > making 2-chip DIMMs, I don't see how you would run 8GB in this box (and 
> > > I have seen it being done under other operating systems).
> > 
> > The Intel AD450NX in in the class ``supporting 8 sockets or more''.
> > The Intel AD450NX is in the class ``high dollar server machines''.
> > 
> > > 
> > > You might want to qualify the issue a little further; specifically with 
> > > regard to "typical memory controllers", logic families and fanout.
> > 
> > I think I qualified it plenty enough...
> > 
> > As far as logic families and fanout, well they really don't matter much
> > with regards to this issue, memory drivers are special, not made with the
> > same configuration that the logic family is, and thus it's fanout is
> > quite different.  The constant has been 72 for a very long time, since I
> > started duing mos memory system designs with 54xx/74xx TTL in the 80's
> > until today with the latest in CMOS and BiCMOS.  Yea.. I could design a
> > supper honking driver that can drive 288 chips in the memory controller,
> > but then all the RAM chips would have to have larger data drivers to
> > handle that side of the bus.
> 
> You could use buffered DIMMs I guess. Not really PC standard stuff though.

If the memory controller was designed to deal with them, or
you use faster DRAM's themselves to compensate for the additional
delay that buffered DIMMS add.  6nS DRAM'S price difference would
probably be more than going from a clone MB to one like the AD450NX
that is designed for large memory modules.

Also buffered DIMMS usually take care of the address line loading issue,
you may still have a problem with the databus drivers in the DRAM chips
being able to drive data back to the CPU.  Buffering both the data and
address lines would push you close to needing 5nS chips. (The address
lines see one package pin of loading for each chip in the whole memory
array, datalines see one, two or four package pin of loading for each
DIMM in the array, dependent on single or double row, normal or low
density dimms.)

-- 
Rod Grimes - KD7CAX - (RWG25)                    rgrimes@gndrsh.dnsmgr.net


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