From owner-svn-src-all@freebsd.org Fri Oct 30 23:00:49 2015 Return-Path: Delivered-To: svn-src-all@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 714E9A21944; Fri, 30 Oct 2015 23:00:49 +0000 (UTC) (envelope-from adrian@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 2E8FC11A0; Fri, 30 Oct 2015 23:00:49 +0000 (UTC) (envelope-from adrian@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id t9UN0mEC098208; Fri, 30 Oct 2015 23:00:48 GMT (envelope-from adrian@FreeBSD.org) Received: (from adrian@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id t9UN0m76098207; Fri, 30 Oct 2015 23:00:48 GMT (envelope-from adrian@FreeBSD.org) Message-Id: <201510302300.t9UN0m76098207@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: adrian set sender to adrian@FreeBSD.org using -f From: Adrian Chadd Date: Fri, 30 Oct 2015 23:00:48 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r290212 - head/sys/mips/atheros X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 30 Oct 2015 23:00:49 -0000 Author: adrian Date: Fri Oct 30 23:00:47 2015 New Revision: 290212 URL: https://svnweb.freebsd.org/changeset/base/290212 Log: arge_mdio: add explicit read barriers for MDIO_READs. The mips74k programmers guide notes that reads can be re-ordered, even uncached ones, so we need an explicit SYNC between them. Yes, this is a case of a driver author actively doing a bus barrier operation. This ends up being necessary when the mips74k core is run in write-back mode rather than write-through mode. That's coming in an upcoming commit. Tested: * mips74k, QCA9558 SoC (AP135 reference board), arge<->arge interface routing traffic tests. Modified: head/sys/mips/atheros/if_arge.c Modified: head/sys/mips/atheros/if_arge.c ============================================================================== --- head/sys/mips/atheros/if_arge.c Fri Oct 30 22:55:41 2015 (r290211) +++ head/sys/mips/atheros/if_arge.c Fri Oct 30 23:00:47 2015 (r290212) @@ -1081,8 +1081,10 @@ arge_miibus_readreg(device_t dev, int ph i = ARGE_MII_TIMEOUT; while ((ARGE_MDIO_READ(sc, AR71XX_MAC_MII_INDICATOR) & - MAC_MII_INDICATOR_BUSY) && (i--)) + MAC_MII_INDICATOR_BUSY) && (i--)) { + ARGE_MDIO_BARRIER_READ(sc); DELAY(5); + } if (i < 0) { mtx_unlock(&miibus_mtx); @@ -1092,6 +1094,7 @@ arge_miibus_readreg(device_t dev, int ph } result = ARGE_MDIO_READ(sc, AR71XX_MAC_MII_STATUS) & MAC_MII_STATUS_MASK; + ARGE_MDIO_BARRIER_READ(sc); ARGE_MDIO_WRITE(sc, AR71XX_MAC_MII_CMD, MAC_MII_CMD_WRITE); mtx_unlock(&miibus_mtx); @@ -1119,8 +1122,10 @@ arge_miibus_writereg(device_t dev, int p i = ARGE_MII_TIMEOUT; while ((ARGE_MDIO_READ(sc, AR71XX_MAC_MII_INDICATOR) & - MAC_MII_INDICATOR_BUSY) && (i--)) + MAC_MII_INDICATOR_BUSY) && (i--)) { + ARGE_MDIO_BARRIER_READ(sc); DELAY(5); + } mtx_unlock(&miibus_mtx);