From owner-p4-projects@FreeBSD.ORG Mon Feb 2 21:54:51 2009 Return-Path: Delivered-To: p4-projects@freebsd.org Received: by hub.freebsd.org (Postfix, from userid 32767) id B207C1065674; Mon, 2 Feb 2009 21:54:51 +0000 (UTC) Delivered-To: perforce@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 6C44D106566C for ; Mon, 2 Feb 2009 21:54:51 +0000 (UTC) (envelope-from marius@freebsd.org) Received: from repoman.freebsd.org (repoman.freebsd.org [IPv6:2001:4f8:fff6::29]) by mx1.freebsd.org (Postfix) with ESMTP id 5922D8FC1F for ; Mon, 2 Feb 2009 21:54:51 +0000 (UTC) (envelope-from marius@freebsd.org) Received: from repoman.freebsd.org (localhost [127.0.0.1]) by repoman.freebsd.org (8.14.3/8.14.3) with ESMTP id n12Lsp1v076592 for ; Mon, 2 Feb 2009 21:54:51 GMT (envelope-from marius@freebsd.org) Received: (from perforce@localhost) by repoman.freebsd.org (8.14.3/8.14.3/Submit) id n12LspKS076590 for perforce@freebsd.org; Mon, 2 Feb 2009 21:54:51 GMT (envelope-from marius@freebsd.org) Date: Mon, 2 Feb 2009 21:54:51 GMT Message-Id: <200902022154.n12LspKS076590@repoman.freebsd.org> X-Authentication-Warning: repoman.freebsd.org: perforce set sender to marius@freebsd.org using -f From: Marius Strobl To: Perforce Change Reviews Cc: Subject: PERFORCE change 157064 for review X-BeenThere: p4-projects@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: p4 projects tree changes List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 02 Feb 2009 21:54:52 -0000 http://perforce.freebsd.org/chv.cgi?CH=157064 Change 157064 by marius@flak on 2009/02/02 21:54:09 Flesh out cas(4); basic support for Cassini+ and Saturn works, Cassini are untested. Affected files ... .. //depot/projects/usiii/dev/cas/if_cas.c#1 add .. //depot/projects/usiii/dev/cas/if_casreg.h#3 edit .. //depot/projects/usiii/dev/cas/if_casvar.h#1 add .. //depot/projects/usiii/dev/mii/nsgphy.c#2 edit Differences ... ==== //depot/projects/usiii/dev/cas/if_casreg.h#3 (text+ko) ==== @@ -13,7 +13,7 @@ * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * - * THIS software IS PROVIDED BY THE AUTHOR ``AS IS'' AND + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE @@ -22,11 +22,11 @@ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS software, EVEN IF ADVISED OF THE POSSIBILITY OF + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * from: NetBSD: gemreg.h,v 1.8 2005/12/11 12:21:26 christos Exp - * from: FreeBSD: head/sys/dev/gem/if_gemvar.h 174987 2007-12-30 01:32:03Z marius + * from: FreeBSD: if_gemvar.h 174987 2007-12-30 01:32:03Z marius * * $FreeBSD$ */ @@ -34,7 +34,10 @@ #ifndef _IF_CASREG_H #define _IF_CASREG_H -/* register definitions for Sun Cassini Gigabit Ethernet */ +/* + * register definitions for Sun Cassini/Cassini+ and National Semiconductor + * DP83065 Saturn Gigabit Ethernet controllers + */ /* glocal resources */ #define CAS_CAW 0x0004 /* core arbitration weight */ @@ -100,7 +103,8 @@ #define CAS_INTR_MIF 0x00020000 /* MIF interrupt */ #define CAS_INTR_PCI_ERROR_INT 0x00040000 /* PCI error interrupt */ -#define CAS_STATUS_TX_COMP3 0xfff80000 /* TX completion 3 */ +#define CAS_STATUS_TX_COMP3_MASK 0xfff80000 /* TX completion 3 */ +#define CAS_STATUS_TX_COMP3_SHFT 19 /* CAS_ERROR_STATUS and CAS_ERROR_MASK PCI error bits */ #define CAS_ERROR_DTRTO 0x00000002 /* delayed trans. timeout */ @@ -125,7 +129,7 @@ #define CAS_RESET_TX 0x00000001 /* Reset TX DMA engine. */ #define CAS_RESET_RX 0x00000002 /* Reset RX DMA engine. */ #define CAS_RESET_RSTOUT 0x00000004 /* Force PCI RSTOUT#. */ -#define CAS_RESET_PCS_DIS 0x00000004 /* PCS reset disable */ +#define CAS_RESET_PCS_DIS 0x00000008 /* PCS reset disable */ #define CAS_RESET_BREQ_SM 0x00007f00 /* breq state machine */ #define CAS_RESET_PCIARB 0x00070000 /* PCI arbitration state */ #define CAS_RESET_RDPCI 0x00300000 /* read PCI state */ @@ -187,16 +191,16 @@ #define CAS_TX_COMP2 0x204c /* TX completion 2 */ #define CAS_TX_COMP3 0x2050 /* TX completion 3 */ #define CAS_TX_COMP4 0x2054 /* TX completion 4 */ -#define CAS_TX_COMP_BASE_WB_LO 0x2058 /* TX completion writeback base low */ -#define CAS_TX_COMP_BASE_WB_HI 0x205c /* TX completion writeback base high */ -#define CAS_TX_DESC_BASE_LO1 0x2060 /* TX descriptor ring base low 1 */ -#define CAS_TX_DESC_BASE_HI1 0x2064 /* TX descriptor ring base high 1 */ -#define CAS_TX_DESC_BASE_LO2 0x2068 /* TX descriptor ring base low 2 */ -#define CAS_TX_DESC_BASE_HI2 0x206c /* TX descriptor ring base high 2 */ -#define CAS_TX_DESC_BASE_LO3 0x2070 /* TX descriptor ring base low 3 */ -#define CAS_TX_DESC_BASE_HI3 0x2074 /* TX descriptor ring base high 3 */ -#define CAS_TX_DESC_BASE_LO4 0x2078 /* TX descriptor ring base low 4 */ -#define CAS_TX_DESC_BASE_HI4 0x207c /* TX descriptor ring base high 4 */ +#define CAS_TX_COMPWB_BASE_LO 0x2058 /* TX completion writeback base low */ +#define CAS_TX_COMPWB_BASE_HI 0x205c /* TX completion writeback base high */ +#define CAS_TX_DESC1_BASE_LO 0x2060 /* TX descriptor ring 1 base low */ +#define CAS_TX_DESC1_BASE_HI 0x2064 /* TX descriptor ring 1 base high */ +#define CAS_TX_DESC2_BASE_LO 0x2068 /* TX descriptor ring 2 base low */ +#define CAS_TX_DESC2_BASE_HI 0x206c /* TX descriptor ring 2 base high */ +#define CAS_TX_DESC3_BASE_LO 0x2070 /* TX descriptor ring 2 base low */ +#define CAS_TX_DESC3_BASE_HI 0x2074 /* TX descriptor ring 2 base high */ +#define CAS_TX_DESC4_BASE_LO 0x2078 /* TX descriptor ring 2 base low */ +#define CAS_TX_DESC4_BASE_HI 0x207c /* TX descriptor ring 2 base high */ #define CAS_TX_MAXBURST1 0x2080 /* TX MaxBurst 1 */ #define CAS_TX_MAXBURST2 0x2084 /* TX MaxBurst 2 */ #define CAS_TX_MAXBURST3 0x2088 /* TX MaxBurst 3 */ @@ -206,7 +210,7 @@ #define CAS_TX_FIFO_DATA_LO 0x210c /* TX FIFO data low */ #define CAS_TX_FIFO_DATA_HI_T1 0x2110 /* TX FIFO data highT1 */ #define CAS_TX_FIFO_DATA_HI_T0 0x2114 /* TX FIFO data highT0 */ -#define CAS_TX_FIFO_SIZE 0x2118 /* TX FIFO size */ +#define CAS_TX_FIFO_SIZE 0x2118 /* TX FIFO size in 64 byte multiples */ #define CAS_TX_RAM_BIST 0x211c /* TX RAM BIST control/status */ #define CAS_TX_CONF_TXDMA_EN 0x00000001 /* TX DMA enable */ @@ -229,6 +233,10 @@ #define CAS_TX_CONF_CTX_MASK 0xc0000000 /* test port selection */ #define CAS_TX_CONF_CTX_SHFT 30 +#define CAS_TX_COMPWB_ALIGN 2048 /* TX compl. W/B alignment */ + +#define CAS_TX_DESC_ALIGN 2048 /* TX descriptor alignment */ + /* descriptor ring size bits for both CAS_TX_CONF and CAS_RX_CONF */ #define CAS_DESC_32 0x0 /* 32 descriptors */ #define CAS_DESC_64 0x1 /* 64 descriptors */ @@ -244,7 +252,7 @@ #define CAS_TX_SM1_CKSUM 0x00000c00 /* checksum state machine */ #define CAS_TX_SM1_TX_FIFO_LOAD 0x0003f000 /* TX FIFO load state machine */ #define CAS_TX_SM1_TX_FIFO_UNLD 0x003c0000 /* TX FIFO unload state mach. */ -#define CAS_TX_SM1_CACHE_CTRL 0x03c00000 /* cache controll state mach. */ +#define CAS_TX_SM1_CACHE_CTRL 0x03c00000 /* cache control state mach. */ #define CAS_TX_SM1_CBQARB 0x03c00000 /* CBQ arbiter state machine */ #define CAS_TX_SM2_COMPWB 0x00000007 /* compl. WB state machine */ @@ -311,14 +319,14 @@ #define CAS_RX_REAS_DMA_DATA_MD 0x4130 /* RX reassembly DMA table data mid */ #define CAS_RX_REAS_DMA_DATA_HI 0x4134 /* RX reassembly DMA table data high */ /* The rest of the RX DMA registers are Cassini+/Saturn only. */ -#define CAS_RX_DESC_BASE_LO2 0x4200 /* RX descriptor ring base low 2 */ -#define CAS_RX_DESC_BASE_HI2 0x4204 /* RX descriptor ring base high 2 */ -#define CAS_RX_COMP_BASE_LO2 0x4208 /* RX completion ring base low 2 */ -#define CAS_RX_COMP_BASE_HI2 0x420c /* RX completion ring base high 2 */ -#define CAS_RX_COMP_BASE_LO3 0x4210 /* RX completion ring base low 3 */ -#define CAS_RX_COMP_BASE_HI3 0x4214 /* RX completion ring base high 3 */ -#define CAS_RX_COMP_BASE_LO4 0x4218 /* RX completion ring base low 4 */ -#define CAS_RX_COMP_BASE_HI4 0x421c /* RX completion ring base high 4 */ +#define CAS_RX_DESC2_BASE_LO 0x4200 /* RX descriptor ring 2 base low */ +#define CAS_RX_DESC2_BASE_HI 0x4204 /* RX descriptor ring 2 base high */ +#define CAS_RX_COMP2_BASE_LO 0x4208 /* RX completion ring 2 base low */ +#define CAS_RX_COMP2_BASE_HI 0x420c /* RX completion ring 2 base high */ +#define CAS_RX_COMP3_BASE_LO 0x4210 /* RX completion ring 3 base low */ +#define CAS_RX_COMP3_BASE_HI 0x4214 /* RX completion ring 3 base high */ +#define CAS_RX_COMP4_BASE_LO 0x4218 /* RX completion ring 4 base low */ +#define CAS_RX_COMP4_BASE_HI 0x421c /* RX completion ring 4 base high */ #define CAS_RX_KICK2 0x4220 /* RX kick 2 */ #define CAS_RX_COMP2 0x4224 /* RX completion 2 */ #define CAS_RX_COMP_HEAD2 0x4228 /* RX completion head 2 */ @@ -338,8 +346,8 @@ #define CAS_RX_CONF_SOFF_MASK 0x00001c00 /* swivel offset */ #define CAS_RX_CONF_SOFF_SHFT 10 /* The RX descriptor ring 2 is Cassini+/Saturn only. */ -#define CAS_RX_CONF_DESC_MASK 0x000f0000 /* RX descriptor ring 2 size */ -#define CAS_RX_CONF_DESC_SHFT 16 +#define CAS_RX_CONF_DESC2_MASK 0x000f0000 /* RX descriptor ring 2 size */ +#define CAS_RX_CONF_DESC2_SHFT 16 #define CAS_RX_CONF_COMP_128 0x0 /* 128 descriptors */ #define CAS_RX_CONF_COMP_256 0x1 /* 256 descriptors */ @@ -375,6 +383,10 @@ #define CAS_RX_PSZ_MB_OFF_96 0x2 /* MTU buf. offset 96 bytes */ #define CAS_RX_PSZ_MB_OFF_128 0x3 /* MTU buf. offset 128 bytes */ +#define CAS_RX_DESC_ALIGN 8192 /* RX descriptor alignment */ + +#define CAS_RX_COMP_ALIGN 8192 /* RX complition alignment */ + /* The RX PAUSE thresholds are specified in multiples of 64 bytes. */ #define CAS_RX_PTHRS_XOFF_MASK 0x000001ff /* XOFF PAUSE */ #define CAS_RX_PTHRS_XOFF_SHFT 0 @@ -389,7 +401,7 @@ */ #define CAS_RX_BLANK_PKTS_MASK 0x000001ff /* RX blanking packets */ #define CAS_RX_BLANK_PKTS_SHFT 0 -#define CAS_RX_BLANK_TIME_MASK 0x3ffff000 /* RX blanking packets */ +#define CAS_RX_BLANK_TIME_MASK 0x3ffff000 /* RX blanking time */ #define CAS_RX_BLANK_TIME_SHFT 12 /* CAS_RX_AEMPTY_THRS and CAS_RX_AEMPTY_THRS2 bits */ @@ -508,8 +520,8 @@ #define CAS_HP_STATUS3_JMBHS_EN 0x00000400 /* jumbo header split enable */ #define CAS_HP_STATUS3_BWO_REAS 0x00000800 /* batching w/o reassembly */ #define CAS_HP_STATUS3_FRC_DROP 0x00001000 /* force drop */ -#define CAS_HP_STATUS3_AR2_MASK 0x000fe000 /* accu_R1 */ -#define CAS_HP_STATUS3_AR2_SHFT 13 +#define CAS_HP_STATUS3_AR1_MASK 0x000fe000 /* accu_R1 */ +#define CAS_HP_STATUS3_AR1_SHFT 13 #define CAS_HP_STATUS3_CSO_MASK 0x07f00000 /* checksum start offset */ #define CAS_HP_STATUS3_CSO_SHFT 19 #define CAS_HP_STATUS3_AR2_MASK 0xf0000000 /* accu_R2[3:0] */ @@ -602,11 +614,11 @@ #define CAS_MAC_ADDR42 0x6128 /* MAC address 42 */ #define CAS_MAC_ADDR43 0x612c /* MAC address 43 */ #define CAS_MAC_ADDR44 0x6130 /* MAC address 44 */ -#define CAS_MAC_ADDR_FILTER0 0x614c /* address filter 0 */ -#define CAS_MAC_ADDR_FILTER1 0x6150 /* address filter 1 */ -#define CAS_MAC_ADDR_FILTER2 0x6154 /* address filter 2 */ -#define CAS_MAC_ADR_FLT_MASK1_2 0x6158 /* address filter 2 & 1 mask*/ -#define CAS_MAC_ADR_FLT_MASK0 0x615c /* address filter 0 mask */ +#define CAS_MAC_AFILTER0 0x614c /* address filter 0 */ +#define CAS_MAC_AFILTER1 0x6150 /* address filter 1 */ +#define CAS_MAC_AFILTER2 0x6154 /* address filter 2 */ +#define CAS_MAC_AFILTER_MASK1_2 0x6158 /* address filter 2 & 1 mask*/ +#define CAS_MAC_AFILTER_MASK0 0x615c /* address filter 0 mask */ #define CAS_MAC_HASH0 0x6160 /* hash table 0 */ #define CAS_MAC_HASH1 0x6164 /* hash table 1 */ #define CAS_MAC_HASH2 0x6168 /* hash table 2 */ @@ -642,7 +654,7 @@ #define CAS_MAC_SPC_SEND 0x00010000 /* Send PAUSE frame. */ /* CAS_MAC_TX_STATUS and CAS_MAC_TX_MASK register bits */ -#define CAS_MAC_TX_FRAME_XMTTD 0x00000001 /* Frame transmitted. */ +#define CAS_MAC_TX_FRAME_XMTD 0x00000001 /* Frame transmitted. */ #define CAS_MAC_TX_UNDERRUN 0x00000002 /* TX data starvation */ #define CAS_MAC_TX_MAX_PKT_ERR 0x00000004 /* frame > CAS_MAC_MAX_FRAME */ #define CAS_MAC_TX_NCC_EXP 0x00000008 /* normal coll. counter wrap */ @@ -881,6 +893,9 @@ #define CAS_PHYAD_INTERNAL 1 #define CAS_PHYAD_EXTERNAL 0 +/* wired RX FIFO size in bytes */ +#define CAS_RX_FIFO_SIZE 16 * 1024 + /* * descriptor ring structures */ @@ -914,10 +929,10 @@ * receive completion ring structure */ struct cas_rx_comp { - uint64_t word1; - uint64_t word2; - uint64_t word3; - uint64_t word4; + uint64_t crc_word1; + uint64_t crc_word2; + uint64_t crc_word3; + uint64_t crc_word4; }; #define CAS_RC1_DATA_SIZE_MASK 0x0000000007ffe000ULL /* pkt. data length */ @@ -968,7 +983,7 @@ #define CAS_RC3_PLUS_L3HO_MASK 0x0000fc0000000000ULL /* layer 3 hdr. off. */ #define CAS_RC3_PLUS_L3HO_SHFT 42 #define CAS_RC3_SAP_MASK 0xffff000000000000ULL /* ethertype */ -#define CAS_RC3_SAP_SHIFT 48 +#define CAS_RC3_SAP_SHFT 48 #define CAS_RC4_TCP_CSUM_MASK 0x000000000000ffffULL /* TCP checksum */ #define CAS_RC4_TCP_CSUM_SHFT 0 @@ -983,4 +998,6 @@ #define CAS_RC4_BAD 0x4000000000000000ULL /* CRC error */ #define CAS_RC4_LEN_MMATCH 0x8000000000000000ULL /* length field mism. */ +#define CAS_GET(reg, bits) (((reg) & (bits ## _MASK)) >> (bits ## _SHFT)) + #endif ==== //depot/projects/usiii/dev/mii/nsgphy.c#2 (text+ko) ==== @@ -38,20 +38,22 @@ */ #include -__FBSDID("$FreeBSD: src/sys/dev/mii/nsgphy.c,v 1.24 2006/12/02 15:32:33 marius Exp $"); +__FBSDID("$FreeBSD: head/sys/dev/mii/nsgphy.c 164827 2006-12-02 15:32:34Z marius $"); /* - * Driver for the National Semiconductor DP83891 and DP83861 + * Driver for the National Semiconductor DP83861, DP83865 and DP83891 * 10/100/1000 PHYs. * Datasheet available at: http://www.national.com/ds/DP/DP83861.pdf + * and at: http://www.national.com/ds/DP/DP83865.pdf * - * The DP83891 is the older NatSemi gigE PHY which isn't being sold - * anymore. The DP83861 is its replacement, which is an 'enhanced' - * firmware driven component. The major difference between the - * two is that the 83891 can't generate interrupts, while the - * 83861 can. (I think it wasn't originally designed to do this, but - * it can now thanks to firmware updates.) The 83861 also allows - * access to its internal RAM via indirect register access. + * The DP83891 is the older NS GigE PHY which isn't being sold + * anymore. The DP83861 is its replacement, which is an 'enhanced' + * firmware driven component. The major difference between the + * two is that the DP83891 can't generate interrupts, while the + * 83861 can (probably it wasn't originally designed to do this, but + * it can now thanks to firmware updates). The DP83861 also allows + * access to its internal RAM via indirect register access. The + * DP83865 is an ultra low power version of the DP83861 and DP83891. */ #include @@ -99,6 +101,7 @@ static const struct mii_phydesc nsgphys[] = { MII_PHY_DESC(NATSEMI, DP83861), + MII_PHY_DESC(NATSEMI, DP83865), MII_PHY_DESC(NATSEMI, DP83891), MII_PHY_END }; @@ -133,8 +136,14 @@ mii->mii_instance++; + mii_phy_reset(sc); + + /* + * NB: the PHY has the 10baseT BMSR bits hard-wired to 0, + * even though it supports 10baseT. + */ sc->mii_capabilities = (PHY_READ(sc, MII_BMSR) | - (BMSR_10TFDX|BMSR_10THDX)) & ma->mii_capmask; + (BMSR_10TFDX | BMSR_10THDX)) & ma->mii_capmask; if (sc->mii_capabilities & BMSR_EXTSTAT) sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); @@ -238,7 +247,7 @@ return; } - switch (physup & (PHY_SUP_SPEED1|PHY_SUP_SPEED0)) { + switch (physup & (PHY_SUP_SPEED1 | PHY_SUP_SPEED0)) { case PHY_SUP_SPEED1: mii->mii_media_active |= IFM_1000_T; gtsr = PHY_READ(sc, MII_100T2SR); @@ -257,9 +266,13 @@ default: mii->mii_media_active |= IFM_NONE; mii->mii_media_status = 0; + return; } + if (physup & PHY_SUP_DUPLEX) mii->mii_media_active |= IFM_FDX; + else + mii->mii_media_active |= IFM_HDX; } else mii->mii_media_active = ife->ifm_media; }