From owner-freebsd-mips@FreeBSD.ORG Thu Sep 29 06:41:49 2011 Return-Path: Delivered-To: freebsd-mips@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 5E067106566C; Thu, 29 Sep 2011 06:41:49 +0000 (UTC) (envelope-from c.jayachandran@gmail.com) Received: from mail-wy0-f182.google.com (mail-wy0-f182.google.com [74.125.82.182]) by mx1.freebsd.org (Postfix) with ESMTP id BCE948FC13; Thu, 29 Sep 2011 06:41:48 +0000 (UTC) Received: by wyj26 with SMTP id 26so99954wyj.13 for ; Wed, 28 Sep 2011 23:41:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; bh=PUHJC2nZ1YecBNuXL7WcdITpUncNMuCqV308DYFCVOw=; b=mQaUqhvHXGLoYp1viwY/IbQhxGLj3dXCDibIIRSnAzfXsDvsOsd1nd8VegfdWCqiZb DkzU0KM8o/8OOvQAmP/7+LeM1YAdAe7LDw2QLZve8OYuIEJoPuLSygooSdcg0yZYpO+e OTherCqWZJsgKb8Ma9mKdf8SU0Z0ohG5sK90g= MIME-Version: 1.0 Received: by 10.216.220.131 with SMTP id o3mr9871811wep.11.1317278507517; Wed, 28 Sep 2011 23:41:47 -0700 (PDT) Received: by 10.216.154.5 with HTTP; Wed, 28 Sep 2011 23:41:47 -0700 (PDT) In-Reply-To: References: Date: Thu, 29 Sep 2011 12:11:47 +0530 Message-ID: From: "Jayachandran C." To: Adrian Chadd Content-Type: text/plain; charset=ISO-8859-1 Cc: freebsd-mips@freebsd.org Subject: Re: eventtimer issue on mips: temporary workaround X-BeenThere: freebsd-mips@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Porting FreeBSD to MIPS List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 29 Sep 2011 06:41:49 -0000 On Wed, Sep 28, 2011 at 10:06 PM, Adrian Chadd wrote: > .. so, the patch is totallyw rong. > > intr_disable() needs to be moved before critical_enter() or it doesn't > achieve anything. I'm not able to figure out why... > But the race is still there, between intr_enable() and "wait". > The only way to eliminate this race is to completely eliminate all the > code in cpu_idle(). the amd implementation seems to be using the STI instruction to enable interrupts - but I'm not able to see how to avoid this race condition on platforms which does not have a similar instruction. > Would someone clued in the implementation of wait please step up and help? :) What if go back to the earlier version of cpu_idle which does not have critical_enter() and cpu_idleclock() for now, or does this also have issues? I had also seen issues on XLR which went away when I took out 'ET_FLAGS_ONESHOT' from the mips clock event timer . That is another possible workaround. JC.