From owner-freebsd-current Sun Jul 26 09:50:53 1998 Return-Path: Received: (from majordom@localhost) by hub.freebsd.org (8.8.8/8.8.8) id JAA09085 for freebsd-current-outgoing; Sun, 26 Jul 1998 09:50:53 -0700 (PDT) (envelope-from owner-freebsd-current@FreeBSD.ORG) Received: from dyson.iquest.net (dyson.iquest.net [198.70.144.127]) by hub.freebsd.org (8.8.8/8.8.8) with ESMTP id JAA09070 for ; Sun, 26 Jul 1998 09:50:48 -0700 (PDT) (envelope-from toor@dyson.iquest.net) Received: (from root@localhost) by dyson.iquest.net (8.8.8/8.8.8) id LAA01167; Sun, 26 Jul 1998 11:49:35 -0500 (EST) (envelope-from toor) Message-Id: <199807261649.LAA01167@dyson.iquest.net> Subject: Re: New LINT options: what is VM coloring? In-Reply-To: <19980726141137.A11215@keltia.freenix.fr> from Ollivier Robert at "Jul 26, 98 02:11:37 pm" To: roberto@keltia.freenix.fr (Ollivier Robert) Date: Sun, 26 Jul 1998 11:49:34 -0500 (EST) Cc: freebsd-current@FreeBSD.ORG From: "John S. Dyson" Reply-To: dyson@iquest.net X-Mailer: ELM [version 2.4ME+ PL38 (25)] MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Sender: owner-freebsd-current@FreeBSD.ORG Precedence: bulk X-Loop: FreeBSD.ORG Ollivier Robert said: > According to David Greenman: > > be a big win for direct-mapped caches (e.g. most Pentium L2 caches), but > > loses effectiveness with set-associative caches (e.g. Pentium Pro, which > > has a set size of 4). > > The K6 has a 2-way set associative cache so I guess it is not interesting > to use page coloring but does anyone know what kind of L2 cache an ASUS T2P4 > use ? It is a P5-class motherboard so it is possible that the cache is > direct-mapped, no ? > David is essentially right. However, the page coloring code (that has been in -current for the last >1yr) goes a little too far and colors even the 1st level cache (I know -- I did it.) Also, there is the issue of proper choice of initial color values, so I used an ad-hoc approach that appears to work correctly most of the time. Almost all P5 MB's use direct mapped 2nd level caches. Only certain of the specialized P5 cache mgr chips do a 4way set assoc scheme. -- John | Never try to teach a pig to sing, dyson@iquest.net | it makes one look stupid jdyson@nc.com | and it irritates the pig. To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe freebsd-current" in the body of the message