From owner-svn-src-all@freebsd.org Fri Jul 3 03:32:54 2015 Return-Path: Delivered-To: svn-src-all@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id CE7F499470B; Fri, 3 Jul 2015 03:32:54 +0000 (UTC) (envelope-from adrian@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id C02E31E1A; Fri, 3 Jul 2015 03:32:54 +0000 (UTC) (envelope-from adrian@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.70]) by repo.freebsd.org (8.14.9/8.14.9) with ESMTP id t633WsA6099679; Fri, 3 Jul 2015 03:32:54 GMT (envelope-from adrian@FreeBSD.org) Received: (from adrian@localhost) by repo.freebsd.org (8.14.9/8.14.9/Submit) id t633WsVP099678; Fri, 3 Jul 2015 03:32:54 GMT (envelope-from adrian@FreeBSD.org) Message-Id: <201507030332.t633WsVP099678@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: adrian set sender to adrian@FreeBSD.org using -f From: Adrian Chadd Date: Fri, 3 Jul 2015 03:32:54 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r285072 - head/sys/mips/atheros X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 03 Jul 2015 03:32:54 -0000 Author: adrian Date: Fri Jul 3 03:32:54 2015 New Revision: 285072 URL: https://svnweb.freebsd.org/changeset/base/285072 Log: Add register defines for the QCA955x DDR flush and GPIO control. Modified: head/sys/mips/atheros/qca955xreg.h Modified: head/sys/mips/atheros/qca955xreg.h ============================================================================== --- head/sys/mips/atheros/qca955xreg.h Fri Jul 3 02:06:47 2015 (r285071) +++ head/sys/mips/atheros/qca955xreg.h Fri Jul 3 03:32:54 2015 (r285072) @@ -179,6 +179,13 @@ #define QCA955X_RESET_I2S BIT(0) /* GPIO block */ +#define QCA955X_GPIO_REG_OUT_FUNC0 0x2c +#define QCA955X_GPIO_REG_OUT_FUNC1 0x30 +#define QCA955X_GPIO_REG_OUT_FUNC2 0x34 +#define QCA955X_GPIO_REG_OUT_FUNC3 0x38 +#define QCA955X_GPIO_REG_OUT_FUNC4 0x3c +#define QCA955X_GPIO_REG_OUT_FUNC5 0x40 +#define QCA955X_GPIO_REG_FUNC 0x6c #define QCA955X_GPIO_COUNT 24 #define QCA955X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000) @@ -204,6 +211,10 @@ #define QCA955X_DDR_REG_FLUSH_USB (AR71XX_APB_BASE + 0xa4) #define QCA955X_DDR_REG_FLUSH_PCIE (AR71XX_APB_BASE + 0xa8) #define QCA955X_DDR_REG_FLUSH_WMAC (AR71XX_APB_BASE + 0xac) +/* PCIe EP */ +#define QCA955X_DDR_REG_FLUSH_SRC1 (AR71XX_APB_BSAE + 0xb0) +/* checksum engine */ +#define QCA955X_DDR_REG_FLUSH_SRC2 (AR71XX_APB_BSAE + 0xb2) /* PCIe control block - relative to PCI_CTRL_BASE0/PCI_CTRL_BASE1 */