From owner-svn-src-all@FreeBSD.ORG Mon Dec 9 11:51:18 2013 Return-Path: Delivered-To: svn-src-all@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id 8070C99A; Mon, 9 Dec 2013 11:51:18 +0000 (UTC) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.freebsd.org (Postfix) with ESMTPS id 6B75C12ED; Mon, 9 Dec 2013 11:51:18 +0000 (UTC) Received: from svn.freebsd.org ([127.0.1.70]) by svn.freebsd.org (8.14.7/8.14.7) with ESMTP id rB9BpIXq075340; Mon, 9 Dec 2013 11:51:18 GMT (envelope-from loos@svn.freebsd.org) Received: (from loos@localhost) by svn.freebsd.org (8.14.7/8.14.7/Submit) id rB9BpIOJ075339; Mon, 9 Dec 2013 11:51:18 GMT (envelope-from loos@svn.freebsd.org) Message-Id: <201312091151.rB9BpIOJ075339@svn.freebsd.org> From: Luiz Otavio O Souza Date: Mon, 9 Dec 2013 11:51:18 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r259126 - head/sys/arm/ti X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.17 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 09 Dec 2013 11:51:18 -0000 Author: loos Date: Mon Dec 9 11:51:17 2013 New Revision: 259126 URL: http://svnweb.freebsd.org/changeset/base/259126 Log: Activate the device before attempt to access any of its registers. Without this change we may end up with a panic (Fatal kernel mode data abort: 'External Non-Linefetch Abort (S)') as described in http://e2e.ti.com/support/arm/sitara_arm/f/791/t/276862.aspx. It is now possible to bring up I2C1 and I2C2 on BBB. Approved by: adrian (mentor) Modified: head/sys/arm/ti/ti_i2c.c Modified: head/sys/arm/ti/ti_i2c.c ============================================================================== --- head/sys/arm/ti/ti_i2c.c Mon Dec 9 11:33:45 2013 (r259125) +++ head/sys/arm/ti/ti_i2c.c Mon Dec 9 11:51:17 2013 (r259126) @@ -1076,20 +1076,20 @@ ti_i2c_attach(device_t dev) goto out; } - /* XXXOMAP3: FIXME get proper revision here */ - /* First read the version number of the I2C module */ - sc->sc_rev = ti_i2c_read_2(sc, I2C_REG_REVNB_HI) & 0xff; - - device_printf(dev, "I2C revision %d.%d\n", sc->sc_rev >> 4, - sc->sc_rev & 0xf); - - /* Activate the H/W */ + /* First we _must_ activate the H/W */ err = ti_i2c_activate(dev); if (err) { device_printf(dev, "ti_i2c_activate failed\n"); goto out; } + /* XXXOMAP3: FIXME get proper revision here */ + /* Read the version number of the I2C module */ + sc->sc_rev = ti_i2c_read_2(sc, I2C_REG_REVNB_HI) & 0xff; + + device_printf(dev, "I2C revision %d.%d\n", sc->sc_rev >> 4, + sc->sc_rev & 0xf); + /* activate the interrupt */ err = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE, NULL, ti_i2c_intr, sc, &sc->sc_irq_h);