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From: Bruce M Simpson <bms@FreeBSD.org>
To: Perforce Change Reviews <perforce@freebsd.org>
Cc: 
Subject: PERFORCE change 100867 for review
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http://perforce.freebsd.org/chv.cgi?CH=100867

Change 100867 by bms@bms_montagne on 2006/07/07 11:45:16

	mips64 -> mips32

Affected files ...

.. //depot/projects/mips2/src/sys/conf/kern.mk#4 edit
.. //depot/projects/mips2/src/sys/mips/include/cpufunc.h#9 edit
.. //depot/projects/mips2/src/sys/mips/mips/tlb.c#2 edit

Differences ...

==== //depot/projects/mips2/src/sys/conf/kern.mk#4 (text+ko) ====

@@ -88,7 +88,7 @@
 .if ${MACHINE_ARCH} == "mips"
 CFLAGS+=	-msoft-float -mno-abicalls -mips32
 # XXX for debugging the build
-CFLAGS+=	-save-temps
+#CFLAGS+=	-save-temps
 INLINE_LIMIT?=	15000
 .endif
 

==== //depot/projects/mips2/src/sys/mips/include/cpufunc.h#9 (text+ko) ====

@@ -104,6 +104,8 @@
 #endif
 }
 
+#if 0	/* XXX mips64 */
+
 #define	MIPS_RDRW64_COP0(n,r)					\
 static __inline u_int64_t					\
 mips_rd_ ## n (void)						\
@@ -133,6 +135,7 @@
 MIPS_RDRW64_COP0(xcontext, MIPS_COP_0_TLB_XCONTEXT);
 
 #undef	MIPS_RDRW64_COP0
+#endif
 
 #define	MIPS_RDRW32_COP0(n,r)					\
 static __inline u_int32_t					\
@@ -164,6 +167,12 @@
 MIPS_RDRW32_COP0(cause, MIPS_COP_0_CAUSE);
 MIPS_RDRW32_COP0(status, MIPS_COP_0_STATUS);
 
+/* XXX: mips32 */
+MIPS_RDRW32_COP0(entrylow, MIPS_COP_0_TLB_LOW);
+MIPS_RDRW32_COP0(entryhi, MIPS_COP_0_TLB_HI);
+MIPS_RDRW32_COP0(pagemask, MIPS_COP_0_TLB_PG_MASK);
+/* xcontext does not exist on mips32 */
+
 #undef	MIPS_RDRW32_COP0
 
 static __inline register_t

==== //depot/projects/mips2/src/sys/mips/mips/tlb.c#2 (text+ko) ====

@@ -115,10 +115,12 @@
 	 */
 	mips_wr_wired(1);
 
+#if 0
 	/*
 	 * Set up page table.
 	 */
-	mips_wr_xcontext((uintptr_t)kptmap);
+	mips_wr_xcontext((uintptr_t)kptmap); /* XXX: mips64 */
+#endif
 }
 
 void
@@ -214,8 +216,12 @@
 	/* Bogus VPN2. */
 	ehi = MIPS_KSEG1_END + 2 * i * PAGE_SIZE;
 	mips_wr_index(i);
+#if 0
 	mips_wr_entrylo0(0);
-	mips_wr_entrylo1(0);
+	mips_wr_entrylo1(0);		/* XXX mips64 */
+#else
+	mips_wr_entrylow(0);
+#endif
 	mips_wr_entryhi(ehi);
 	mips_tlbwi();
 }