From owner-freebsd-arm@FreeBSD.ORG Wed Dec 26 09:34:43 2012 Return-Path: Delivered-To: freebsd-arm@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [69.147.83.52]) by hub.freebsd.org (Postfix) with ESMTP id 64A63564 for ; Wed, 26 Dec 2012 09:34:43 +0000 (UTC) (envelope-from aoyama@peach.ne.jp) Received: from moon.peach.ne.jp (moon.peach.ne.jp [203.141.148.98]) by mx1.freebsd.org (Postfix) with ESMTP id C3F1C8FC0A for ; Wed, 26 Dec 2012 09:34:42 +0000 (UTC) Received: from moon.peach.ne.jp (localhost [127.0.0.1]) by moon.peach.ne.jp (Postfix) with ESMTP id 800E539FA3; Wed, 26 Dec 2012 18:34:34 +0900 (JST) Received: from artemis (unknown [172.18.0.20]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (No client certificate requested) by moon.peach.ne.jp (Postfix) with ESMTPSA id 6B42939D5E; Wed, 26 Dec 2012 18:34:34 +0900 (JST) Message-ID: <68E7D970E6D2475C8061DB45301103AF@ad.peach.ne.jp> From: "Daisuke Aoyama" To: "Oleksandr Tymoshenko" References: In-Reply-To: Subject: Re: FreeBSD/armv6z/clang on Raspberry Pi 512MB (with U-Boot + ubldr) Date: Wed, 26 Dec 2012 18:34:30 +0900 MIME-Version: 1.0 Content-Type: text/plain; format=flowed; charset="iso-8859-1"; reply-type=original Content-Transfer-Encoding: 7bit X-Priority: 3 X-MSMail-Priority: Normal Importance: Normal X-Mailer: Microsoft Windows Live Mail 14.0.8117.416 X-MimeOLE: Produced By Microsoft MimeOLE V14.0.8117.416 X-Virus-Scanned: ClamAV using ClamSMTP Cc: freebsd-arm@freebsd.org X-BeenThere: freebsd-arm@freebsd.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: Porting FreeBSD to the StrongARM Processor List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 26 Dec 2012 09:34:43 -0000 >Thanks! I'll integrate timer-related bits later this week, good catch! >spinlock_enter and spinlock_exit are intended to be used only in >spinlock code and should be replaced by intr_disable/intr_restore there, >AFAIU, Yes, you are right. It should not divide/re-entry. It seems the kernel is very stable than any previous! >The other bit I'm considering for merge is armv6 instruction for managing >interrupts/status. Probably, it's unnecessary. It's my cut and try code. RPI is my first ARM architecture for kernel side. Of course, I didn't know about ARM assembler until I got RPI. >PTE sync - related part, Im not sure it's strictly required. We use WT >caches for page tables >so we should be OK without implicit sync operations for them. I hope >somebody >more clueful can confirm/disprove this. It seems CF_ICACHE_SYNC solve PTE problem. Please see arm/swtch.S in the patch. However, still USB LAN is unstable :( Here is current using patch: http://www.peach.ne.jp/archives/rpi/patch/src-244663-20121226.patch.gz If you already have clang world, you can use pre-build version: http://www.peach.ne.jp/archives/rpi/test/kernel-20121226.gz or apply patch and rebuild the kernel yourself. # fetch -o /usr http://www.peach.ne.jp/archives/rpi/patch/src-244663-20121226.patch.gz # cd /usr/src # gzcat /usr/src-244663-20121226.patch.gz | patch # make buildkernel KERNCONF=RPI-B-test9 WITH_FDT=yes Don't forget to add NO_WERROR= and WERROR= to /etc/make.conf if you use clang. If you already applied previous patch, you can remove it by: # cd /usr/src # gzcat /usr/src-244663-20121225.patch.gz | patch -R then, apply new patch. Thanks. -- Daisuke Aoyama