From owner-freebsd-current Sat Aug 17 13:51:03 1996 Return-Path: owner-current Received: (from root@localhost) by freefall.freebsd.org (8.7.5/8.7.3) id NAA17804 for current-outgoing; Sat, 17 Aug 1996 13:51:03 -0700 (PDT) Received: from irz301.inf.tu-dresden.de (irz301.inf.tu-dresden.de [141.76.1.11]) by freefall.freebsd.org (8.7.5/8.7.3) with SMTP id NAA17796 for ; Sat, 17 Aug 1996 13:50:59 -0700 (PDT) Received: from sax.sax.de (sax.sax.de [193.175.26.33]) by irz301.inf.tu-dresden.de (8.6.12/8.6.12-s1) with ESMTP id WAA18338; Sat, 17 Aug 1996 22:50:46 +0200 Received: (from uucp@localhost) by sax.sax.de (8.6.12/8.6.12-s1) with UUCP id WAA17222; Sat, 17 Aug 1996 22:50:45 +0200 Received: (from j@localhost) by uriah.heep.sax.de (8.7.5/8.6.9) id WAA01189; Sat, 17 Aug 1996 22:44:16 +0200 (MET DST) From: J Wunsch Message-Id: <199608172044.WAA01189@uriah.heep.sax.de> Subject: Re: 82439HX registerdump patch To: freebsd-current@FreeBSD.org (FreeBSD-current users) Date: Sat, 17 Aug 1996 22:44:14 +0200 (MET DST) Cc: staff@kyklopen.ping.dk In-Reply-To: from Thomas Sparrevohn at "Aug 17, 96 05:20:35 pm" X-Phone: +49-351-2012 669 X-PGP-Fingerprint: DC 47 E6 E4 FF A6 E9 8F 93 21 E0 7D F9 12 D6 4E X-Mailer: ELM [version 2.4ME+ PL17 (25)] MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Sender: owner-current@FreeBSD.org X-Loop: FreeBSD.org Precedence: bulk As Thomas Sparrevohn wrote: > + { 0x00, 0x00, 0x00, M_TR, ",\n\tDRAM Refrest Rate " }, Refresh Here's my dmesg output, it's an ASUS P/I-P55T2P4 board. Btw., i had to bump the message buffer size to two pages -- David, didn't we intend to make this the default? chip0 rev 1 on pci0:0 DRAM ECC/Parity: ECC, ECC Test disabled, Shutdown to Port 92 disabled, Dual Processor NA# disabled, Peer Concurrency enabled, SERR# Output Type: Open drain output, Global TXC enabled Cache: 512K dual-bank pipelined-burst, NA Disable: disabled, Extended Cacheability disabled, SCFMI disabled, L1 enabled Speculative Leadoff disabled, Turn-around Insertion disabled, Memory Address Drive Strength: 8mA/8mA, 64 Mbit mode disabled Hole: None, EDO Detect mode disabled, DRAM Refrest Rate 66Mhz Turbo Read Leadoff disabled, DRAM Read Burst Timing: x-3-3-3/x-4-4-4, DRAM Write Burst Timing: x-3-3-3, Fast RAS to CAS Delay: 3 clocks, DRAM leadoff Timing: Read 7, Write 6, Precharge 4, Refresh 5 -- cheers, J"org joerg_wunsch@uriah.heep.sax.de -- http://www.sax.de/~joerg/ -- NIC: JW11-RIPE Never trust an operating system you don't have sources for. ;-)