From owner-svn-src-head@freebsd.org Sun Nov 5 16:52:55 2017 Return-Path: Delivered-To: svn-src-head@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id E0E9AE4B018; Sun, 5 Nov 2017 16:52:55 +0000 (UTC) (envelope-from mmel@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id A5F5121DB; Sun, 5 Nov 2017 16:52:55 +0000 (UTC) (envelope-from mmel@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id vA5GqsFR066325; Sun, 5 Nov 2017 16:52:54 GMT (envelope-from mmel@FreeBSD.org) Received: (from mmel@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id vA5GqswC066323; Sun, 5 Nov 2017 16:52:54 GMT (envelope-from mmel@FreeBSD.org) Message-Id: <201711051652.vA5GqswC066323@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: mmel set sender to mmel@FreeBSD.org using -f From: Michal Meloun Date: Sun, 5 Nov 2017 16:52:54 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r325438 - head/sys/arm/include X-SVN-Group: head X-SVN-Commit-Author: mmel X-SVN-Commit-Paths: head/sys/arm/include X-SVN-Commit-Revision: 325438 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 05 Nov 2017 16:52:56 -0000 Author: mmel Date: Sun Nov 5 16:52:54 2017 New Revision: 325438 URL: https://svnweb.freebsd.org/changeset/base/325438 Log: All CP15 registers are bit fields or counters, don't use signed type when accessing them. MFC after: 3 weeks Modified: head/sys/arm/include/cpu-v4.h head/sys/arm/include/cpu-v6.h Modified: head/sys/arm/include/cpu-v4.h ============================================================================== --- head/sys/arm/include/cpu-v4.h Sun Nov 5 16:28:05 2017 (r325437) +++ head/sys/arm/include/cpu-v4.h Sun Nov 5 16:52:54 2017 (r325438) @@ -51,10 +51,10 @@ #define _FX(s...) #s #define _RF0(fname, aname...) \ -static __inline register_t \ +static __inline uint32_t \ fname(void) \ { \ - register_t reg; \ + uint32_t reg; \ __asm __volatile("mrc\t" _FX(aname): "=r" (reg)); \ return(reg); \ } @@ -77,7 +77,7 @@ fname(void) \ #define _WF1(fname, aname...) \ static __inline void \ -fname(register_t reg) \ +fname(uint32_t reg) \ { \ __asm __volatile("mcr\t" _FX(aname):: "r" (reg)); \ } Modified: head/sys/arm/include/cpu-v6.h ============================================================================== --- head/sys/arm/include/cpu-v6.h Sun Nov 5 16:28:05 2017 (r325437) +++ head/sys/arm/include/cpu-v6.h Sun Nov 5 16:52:54 2017 (r325438) @@ -103,10 +103,10 @@ extern int pmu_attched; #define _FX(s...) #s #define _RF0(fname, aname...) \ -static __inline register_t \ +static __inline uint32_t \ fname(void) \ { \ - register_t reg; \ + uint32_t reg; \ __asm __volatile("mrc\t" _FX(aname): "=r" (reg)); \ return(reg); \ } @@ -129,7 +129,7 @@ fname(void) \ #define _WF1(fname, aname...) \ static __inline void \ -fname(register_t reg) \ +fname(uint32_t reg) \ { \ __asm __volatile("mcr\t" _FX(aname):: "r" (reg)); \ }