Date: Wed, 03 Dec 1997 17:28:22 -0700 From: Steve Passe <smp@csn.net> To: Joe Eykholt <jre@Ipsilon.COM> Cc: smp@freebsd.org Subject: Re: SMP Message-ID: <199712040028.RAA10221@Ilsa.StevesCafe.com> In-Reply-To: Your message of "Wed, 03 Dec 1997 16:24:49 PST." <3485F851.3F54BC7E@ipsilon.com>
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Hi, > > Have you actually demonstrated this to occur all times? Or just ocassionally? > > OR just via code examination? Could you descibe a specific example that would > > help me grok the specific situation? > > I think so. I added a counter for interrupts deferred due to cpl and > that > counter was 1/2 the total interrupt count (I counted all interrupts > whether > deferred or not). All my interrupts were PCI devices (level sensitive), > so > I'm pretty sure that's what's happening. I also saw a stack trace that > showed > that the second interrupt occurred just after the first handler did the > sti > instruction. > > I've made other changes to the INTR() macro, but I think the same thing > would > happen in the -current APIC version. thanx, I'll look at this tomorrow... -- Steve Passe | powered by smp@csn.net | Symmetric MultiProcessor FreeBSD
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