From owner-freebsd-smp Wed Dec 3 16:28:29 1997 Return-Path: Received: (from root@localhost) by hub.freebsd.org (8.8.7/8.8.7) id QAA27070 for smp-outgoing; Wed, 3 Dec 1997 16:28:29 -0800 (PST) (envelope-from owner-freebsd-smp) Received: from Ilsa.StevesCafe.com (Ilsa.StevesCafe.com [205.168.119.129]) by hub.freebsd.org (8.8.7/8.8.7) with ESMTP id QAA27064 for ; Wed, 3 Dec 1997 16:28:26 -0800 (PST) (envelope-from smp@Ilsa.StevesCafe.com) Received: from Ilsa.StevesCafe.com (localhost [127.0.0.1]) by Ilsa.StevesCafe.com (8.8.7/8.8.5) with ESMTP id RAA10221; Wed, 3 Dec 1997 17:28:23 -0700 (MST) Message-Id: <199712040028.RAA10221@Ilsa.StevesCafe.com> X-Mailer: exmh version 2.0gamma 1/27/96 From: Steve Passe To: Joe Eykholt cc: smp@freebsd.org Subject: Re: SMP In-reply-to: Your message of "Wed, 03 Dec 1997 16:24:49 PST." <3485F851.3F54BC7E@ipsilon.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Date: Wed, 03 Dec 1997 17:28:22 -0700 Sender: owner-freebsd-smp@freebsd.org X-Loop: FreeBSD.org Precedence: bulk Hi, > > Have you actually demonstrated this to occur all times? Or just ocassionally? > > OR just via code examination? Could you descibe a specific example that would > > help me grok the specific situation? > > I think so. I added a counter for interrupts deferred due to cpl and > that > counter was 1/2 the total interrupt count (I counted all interrupts > whether > deferred or not). All my interrupts were PCI devices (level sensitive), > so > I'm pretty sure that's what's happening. I also saw a stack trace that > showed > that the second interrupt occurred just after the first handler did the > sti > instruction. > > I've made other changes to the INTR() macro, but I think the same thing > would > happen in the -current APIC version. thanx, I'll look at this tomorrow... -- Steve Passe | powered by smp@csn.net | Symmetric MultiProcessor FreeBSD