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Date:      Sun, 28 Mar 2010 02:21:58 +0000 (UTC)
From:      Juli Mallett <jmallett@FreeBSD.org>
To:        src-committers@freebsd.org, svn-src-user@freebsd.org
Subject:   svn commit: r205785 - in user/jmallett/octeon/sys/mips: include mips
Message-ID:  <201003280221.o2S2LwV7070546@svn.freebsd.org>
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Author: jmallett
Date: Sun Mar 28 02:21:58 2010
New Revision: 205785
URL: http://svn.freebsd.org/changeset/base/205785

Log:
  o) Remove some files we don't use yet.  If we end up needing something like
     them, we can evaluate what to use.
  o) Remove the two references to the R3K-style TLB since we don't and don't plan
     to support it AFAIK.
  o) Expose TLB CP0 registers as 64-bit on n64.

Deleted:
  user/jmallett/octeon/sys/mips/include/archtype.h
  user/jmallett/octeon/sys/mips/include/rm7000.h
Modified:
  user/jmallett/octeon/sys/mips/include/cpufunc.h
  user/jmallett/octeon/sys/mips/include/cpuregs.h
  user/jmallett/octeon/sys/mips/mips/trap.c

Modified: user/jmallett/octeon/sys/mips/include/cpufunc.h
==============================================================================
--- user/jmallett/octeon/sys/mips/include/cpufunc.h	Sun Mar 28 01:45:26 2010	(r205784)
+++ user/jmallett/octeon/sys/mips/include/cpufunc.h	Sun Mar 28 02:21:58 2010	(r205785)
@@ -87,10 +87,6 @@ mips_wbflush(void)
 {
 	__asm __volatile ("sync" : : : "memory");
 	mips_barrier();
-#if 0
-	__asm __volatile("mtc0 %0, $12\n" /* MIPS_COP_0_STATUS */
-	   : : "r" (flag));
-#endif
 }
 
 static __inline void
@@ -112,16 +108,6 @@ mips_tlbp(void)
 {
 	__asm __volatile ("tlbp");
 	mips_barrier();
-#if 0
-	register_t ret;
-	register_t tmp;
-
-	__asm __volatile("mfc0	%0, $12\n" /* MIPS_COP_0_STATUS */
-	 		 "and	%1, %0, $~1\n" /* MIPS_SR_INT_IE */
-			 "mtc0	%1, $12\n" /* MIPS_COP_0_STATUS */
-			 : "=r" (ret), "=r" (tmp));
-	return (ret);
-#endif
 }
 
 static __inline void
@@ -136,12 +122,6 @@ mips_tlbwi(void)
 {
 	__asm __volatile ("tlbwi");
 	mips_barrier();
-#if 0
-	__asm __volatile("mfc %0, $12\n" /* MIPS_COP_0_STATUS */
-	    		 "or  %0, %0, $1\n" /* MIPS_SR_INT_IE */
-			 "mtc0 %0, $12\n" /* MIPS_COP_0_STATUS */
-			 : "=r" (tmp));
-#endif
 }
 
 static __inline void
@@ -152,8 +132,7 @@ mips_tlbwr(void)
 }
 
 
-#if 0	/* XXX mips64 */
-
+#if defined(__mips_n32) || defined(__mips_n64)
 #define	MIPS_RDRW64_COP0(n,r)					\
 static __inline uint64_t					\
 mips_rd_ ## n (void)						\
@@ -176,10 +155,12 @@ mips_wr_ ## n (uint64_t a0)					\
 	mips_barrier();						\
 } struct __hack
 
+#if defined(__mips_n64)
 MIPS_RDRW64_COP0(entrylo0, MIPS_COP_0_TLB_LO0);
 MIPS_RDRW64_COP0(entrylo1, MIPS_COP_0_TLB_LO1);
 MIPS_RDRW64_COP0(entryhi, MIPS_COP_0_TLB_HI);
 MIPS_RDRW64_COP0(pagemask, MIPS_COP_0_TLB_PG_MASK);
+#endif
 MIPS_RDRW64_COP0(xcontext, MIPS_COP_0_TLB_XCONTEXT);
 
 #undef	MIPS_RDRW64_COP0
@@ -254,11 +235,12 @@ MIPS_RDRW32_COP0(cause, MIPS_COP_0_CAUSE
 MIPS_RDRW32_COP0(status, MIPS_COP_0_STATUS);
 
 /* XXX: Some of these registers are specific to MIPS32. */
+#if !defined(__mips_n64)
 MIPS_RDRW32_COP0(entrylo0, MIPS_COP_0_TLB_LO0);
 MIPS_RDRW32_COP0(entrylo1, MIPS_COP_0_TLB_LO1);
-MIPS_RDRW32_COP0(entrylow, MIPS_COP_0_TLB_LOW);
 MIPS_RDRW32_COP0(entryhi, MIPS_COP_0_TLB_HI);
 MIPS_RDRW32_COP0(pagemask, MIPS_COP_0_TLB_PG_MASK);
+#endif
 MIPS_RDRW32_COP0(prid, MIPS_COP_0_PRID);
 MIPS_RDRW32_COP0(watchlo, MIPS_COP_0_WATCH_LO);
 MIPS_RDRW32_COP0_SEL(watchlo, MIPS_COP_0_WATCH_LO, 1);

Modified: user/jmallett/octeon/sys/mips/include/cpuregs.h
==============================================================================
--- user/jmallett/octeon/sys/mips/include/cpuregs.h	Sun Mar 28 01:45:26 2010	(r205784)
+++ user/jmallett/octeon/sys/mips/include/cpuregs.h	Sun Mar 28 02:21:58 2010	(r205785)
@@ -490,7 +490,6 @@
  *				     (3=32bit, 6=64bit, i=impl dep)
  *  0	MIPS_COP_0_TLB_INDEX	3333 TLB Index.
  *  1	MIPS_COP_0_TLB_RANDOM	3333 TLB Random.
- *  2	MIPS_COP_0_TLB_LOW	3... r3k TLB entry low.
  *  2	MIPS_COP_0_TLB_LO0	.636 r4k TLB entry low.
  *  3	MIPS_COP_0_TLB_LO1	.636 r4k TLB entry low, extended.
  *  4	MIPS_COP_0_TLB_CONTEXT	3636 TLB Context.
@@ -550,10 +549,6 @@
 #define	MIPS_COP_0_EXC_PC	_(14)
 #define	MIPS_COP_0_PRID		_(15)
 
-
-/* MIPS-I */
-#define	MIPS_COP_0_TLB_LOW	_(2)
-
 /* MIPS-III */
 #define	MIPS_COP_0_TLB_LO0	_(2)
 #define	MIPS_COP_0_TLB_LO1	_(3)

Modified: user/jmallett/octeon/sys/mips/mips/trap.c
==============================================================================
--- user/jmallett/octeon/sys/mips/mips/trap.c	Sun Mar 28 01:45:26 2010	(r205784)
+++ user/jmallett/octeon/sys/mips/mips/trap.c	Sun Mar 28 02:21:58 2010	(r205785)
@@ -83,8 +83,6 @@ __FBSDID("$FreeBSD$");
 #include <machine/mips_opcode.h>
 #include <machine/frame.h>
 #include <machine/regnum.h>
-#include <machine/rm7000.h>
-#include <machine/archtype.h>
 #include <machine/asm.h>
 
 #ifdef DDB

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