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Subject: Re: CACHE_LINE_SIZE macro.
From: Stanislav Sedov <stas@freebsd.org>
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Date: Mon, 5 Nov 2012 09:01:09 -0800
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On Nov 5, 2012, at 8:49 AM, Warner Losh <imp@bsdimp.com> wrote:
>=20
> Is that an out-of-kernel interface?
>=20
> If we did that, we'd have to make it run-time settable, because =
there's no one right answer for arm and MIPS cpus: they are all =
different.
>=20

IIRC, several linux application use getconf to retrieve the host CPU =
cache line
value at the compile time to use for the alignment.  I don't really like =
this
solution as it makes the binaries unportable between different CPUs.

OTOH, it looks like at least for ARM all cpus with a certain ARM core =
share the
same cache line size, and we don't guarantee that e.g. ARMv5 executable =
will
be able to run on ARMv7 without performance penalty.  So it might be a =
good
solution for ARM.  I don't know about MIPS though.

--
ST4096-RIPE