Date: Mon, 4 Feb 2008 08:43:55 GMT From: "Randall R. Stewart" <rrs@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 134769 for review Message-ID: <200802040843.m148htF0037992@repoman.freebsd.org>
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http://perforce.freebsd.org/chv.cgi?CH=134769 Change 134769 by rrs@rrs-mips2-jnpr on 2008/02/04 08:43:01 Ok, It still works but now uses the correct registers. Now, only question I have is if the MCR is used properly. What was being done before does not match any valid register need to figure out what its trying to do with the ioctl. There may be other strange things like this too. Need to go through the driver and look for other strange things. Affected files ... .. //depot/projects/mips2-jnpr/src/sys/mips/conf/OCTEON_rrs#9 edit .. //depot/projects/mips2-jnpr/src/sys/mips/mips/swtch.S#11 edit .. //depot/projects/mips2-jnpr/src/sys/mips/mips32/octeon32/uart_dev_oct16550.c#4 edit Differences ... ==== //depot/projects/mips2-jnpr/src/sys/mips/conf/OCTEON_rrs#9 (text+ko) ==== @@ -33,7 +33,7 @@ makeoptions DEBUG=-g #Build kernel with gdb(1) debug symbols -options ISA_MIPS32 +options ISA_MIPS64 options CPU_NOFPU options DDB @@ -79,6 +79,6 @@ # # Use the following for RFS in mem-device -options MD_ROOT +#options MD_ROOT # options ROOTDEVNAME = \"ufs:md0\" -options MD_ROOT_SIZE = 25200 +#options MD_ROOT_SIZE = 25200 ==== //depot/projects/mips2-jnpr/src/sys/mips/mips/swtch.S#11 (text+ko) ==== ==== //depot/projects/mips2-jnpr/src/sys/mips/mips32/octeon32/uart_dev_oct16550.c#4 (text+ko) ==== @@ -69,16 +69,13 @@ #include <dev/uart/uart_cpu.h> #include <dev/uart/uart_bus.h> -#include <dev/ic/ns16550.h> +#include <mips/mips32/octeon32/oct16550.h> /* Octeon specific includes with loads of in-lines */ #include <mips/mips32/octeon32/octeon_pcmap_regs.h> #include <mips/mips32/octeon32/bus_octeon.h> /* Cavium specific defines pulled from there update of ns16559.h */ -#define IIR_BUSY 0x7 -#define com_usr 39 /* Octeon 16750/16550 Uart Status Reg */ -#define REG_USR com_usr #define USR_TXFIFO_NOTFULL 2 /* Uart TX FIFO Not full */ #include "uart_if.h" @@ -98,19 +95,19 @@ { uint8_t iir; - iir = uart_getreg(bas, REG_IIR); + iir = uart_getreg(bas, OCT_REG_IIR); while ((iir & IIR_NOPEND) == 0) { iir &= IIR_IMASK; if (iir == IIR_RLS) - (void)uart_getreg(bas, REG_LSR); + (void)uart_getreg(bas, OCT_REG_LSR); else if (iir == IIR_RXRDY || iir == IIR_RXTOUT) - (void)uart_getreg(bas, REG_DATA); + (void)uart_getreg(bas, OCT_REG_RBR); else if (iir == IIR_MLSC) - (void)uart_getreg(bas, REG_MSR); + (void)uart_getreg(bas, OCT_REG_MSR); else if (iir == IIR_BUSY) - (void)uart_getreg(bas, REG_USR); + (void)uart_getreg(bas, OCT_REG_USR); uart_barrier(bas); - iir = uart_getreg(bas, REG_IIR); + iir = uart_getreg(bas, OCT_REG_IIR); } } @@ -126,12 +123,12 @@ if (!delay_changed) return delay; delay_changed = 0; - lcr = uart_getreg(bas, REG_LCR); - uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); + lcr = uart_getreg(bas, OCT_REG_LCR); + uart_setreg(bas, OCT_REG_LCR, lcr | LCR_DLAB); uart_barrier(bas); - divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8); + divisor = uart_getreg(bas, OCT_REG_DLL) | (uart_getreg(bas, OCT_REG_DLH) << 8); uart_barrier(bas); - uart_setreg(bas, REG_LCR, lcr); + uart_setreg(bas, OCT_REG_LCR, lcr); uart_barrier(bas); if (!bas->rclk) @@ -182,7 +179,7 @@ * high enough to handle large FIFOs. */ limit = 10 * 10 * 10 * 1024; - while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) + while ((uart_getreg(bas, OCT_REG_LSR) & LSR_TEMT) == 0 && --limit) DELAY(delay); if (limit == 0) { /* @@ -202,8 +199,8 @@ * UART is first activated. */ limit = 10 * 4096; - while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) { - (void)uart_getreg(bas, REG_DATA); + while ((uart_getreg(bas, OCT_REG_LSR) & LSR_RXRDY) && --limit) { + (void)uart_getreg(bas, OCT_REG_RBR); uart_barrier(bas); DELAY(delay << 2); } @@ -229,7 +226,7 @@ fcr |= FCR_XMT_RST; if (what & UART_FLUSH_RECEIVER) fcr |= FCR_RCV_RST; - uart_setreg(bas, REG_FCR, fcr); + uart_setreg(bas, OCT_REG_FCR, fcr); uart_barrier(bas); } @@ -258,15 +255,15 @@ divisor = oct16550_divisor(bas->rclk, baudrate); if (divisor == 0) return (EINVAL); - uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); + uart_setreg(bas, OCT_REG_LCR, lcr | LCR_DLAB); uart_barrier(bas); - uart_setreg(bas, REG_DLL, divisor & 0xff); - uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff); + uart_setreg(bas, OCT_REG_DLL, divisor & 0xff); + uart_setreg(bas, OCT_REG_DLH, (divisor >> 8) & 0xff); uart_barrier(bas); delay_changed = 1; } /* Set LCR and clear DLAB. */ - uart_setreg(bas, REG_LCR, lcr); + uart_setreg(bas, OCT_REG_LCR, lcr); uart_barrier(bas); return (0); } @@ -296,13 +293,13 @@ u_char val; /* Check known 0 bits that don't depend on DLAB. */ - val = uart_getreg(bas, REG_IIR); + val = uart_getreg(bas, OCT_REG_IIR); if (val & 0x30) return (ENXIO); - val = uart_getreg(bas, REG_MCR); + val = uart_getreg(bas, OCT_REG_MCR); if (val & 0xc0) return (ENXIO); - val = uart_getreg(bas, REG_USR); + val = uart_getreg(bas, OCT_REG_USR); if (val & 0xe0) return (ENXIO); return (0); @@ -317,16 +314,16 @@ oct16550_param(bas, baudrate, databits, stopbits, parity); /* Disable all interrupt sources. */ - ier = uart_getreg(bas, REG_IER) & 0x0; - uart_setreg(bas, REG_IER, ier); + ier = uart_getreg(bas, OCT_REG_IER) & 0x0; + uart_setreg(bas, OCT_REG_IER, ier); uart_barrier(bas); /* Disable the FIFO (if present). */ - //uart_setreg(bas, REG_FCR, 0); + //uart_setreg(bas, OCT_REG_FCR, 0); uart_barrier(bas); /* Set RTS & DTR. */ - uart_setreg(bas, REG_MCR, MCR_RTS | MCR_DTR); + uart_setreg(bas, OCT_REG_MCR, MCR_RTS | MCR_DTR); uart_barrier(bas); oct16550_clrint(bas); @@ -337,17 +334,17 @@ { /* Clear RTS & DTR. */ - uart_setreg(bas, REG_MCR, 0); + uart_setreg(bas, OCT_REG_MCR, 0); uart_barrier(bas); } static inline void oct16550_wait_txhr_empty(struct uart_bas *bas, int limit, int delay) { - while (((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0) && - ((uart_getreg(bas, REG_USR) & USR_TXFIFO_NOTFULL) == 0) && --limit) + while (((uart_getreg(bas, OCT_REG_LSR) & LSR_THRE) == 0) && + ((uart_getreg(bas, OCT_REG_USR) & USR_TX_FIFO_NOTFULL) == 0) && --limit) DELAY(delay); -} +} static void oct16550_putc(struct uart_bas *bas, int c) @@ -357,7 +354,7 @@ /* 1/10th the time to transmit 1 character (estimate). */ delay = oct16550_delay(bas); oct16550_wait_txhr_empty(bas, 100, delay); - uart_setreg(bas, REG_DATA, c); + uart_setreg(bas, OCT_REG_THR, c); uart_barrier(bas); oct16550_wait_txhr_empty(bas, 100, delay); } @@ -366,7 +363,7 @@ oct16550_rxready(struct uart_bas *bas) { - return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0); + return ((uart_getreg(bas, OCT_REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0); } static int @@ -379,13 +376,13 @@ /* 1/10th the time to transmit 1 character (estimate). */ delay = oct16550_delay(bas); - while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) { + while ((uart_getreg(bas, OCT_REG_LSR) & LSR_RXRDY) == 0) { uart_unlock(hwmtx); DELAY(delay); uart_lock(hwmtx); } - c = uart_getreg(bas, REG_DATA); + c = uart_getreg(bas, OCT_REG_RBR); uart_unlock(hwmtx); @@ -456,9 +453,9 @@ bas = &sc->sc_bas; oct16550_drain(bas, UART_DRAIN_TRANSMITTER); - oct16550->mcr = uart_getreg(bas, REG_MCR); - oct16550->fcr = FCR_ENABLE | FCR_RX_HIGH; - uart_setreg(bas, REG_FCR, oct16550->fcr); + oct16550->mcr = uart_getreg(bas, OCT_REG_MCR); + oct16550->fcr = FCR_ENABLE | FCR_RX_MEDH; + uart_setreg(bas, OCT_REG_FCR, oct16550->fcr); uart_barrier(bas); oct16550_bus_flush(sc, UART_FLUSH_RECEIVER | UART_FLUSH_TRANSMITTER); @@ -469,9 +466,9 @@ oct16550_bus_getsig(sc); oct16550_clrint(bas); - oct16550->ier = uart_getreg(bas, REG_IER) & 0xf0; + oct16550->ier = uart_getreg(bas, OCT_REG_IER) & 0xf0; oct16550->ier |= IER_EMSC | IER_ERLS | IER_ERXRDY; - uart_setreg(bas, REG_IER, oct16550->ier); + uart_setreg(bas, OCT_REG_IER, oct16550->ier); uart_barrier(bas); /* @@ -489,8 +486,8 @@ u_char ier; bas = &sc->sc_bas; - ier = uart_getreg(bas, REG_IER) & 0xf0; - uart_setreg(bas, REG_IER, ier); + ier = uart_getreg(bas, OCT_REG_IER) & 0xf0; + uart_setreg(bas, OCT_REG_IER, ier); uart_barrier(bas); oct16550_clrint(bas); return (0); @@ -507,7 +504,7 @@ uart_lock(sc->sc_hwmtx); if (sc->sc_rxfifosz > 1) { oct16550_flush(bas, what); - uart_setreg(bas, REG_FCR, oct16550->fcr); + uart_setreg(bas, OCT_REG_FCR, oct16550->fcr); uart_barrier(bas); error = 0; } else @@ -526,7 +523,7 @@ old = sc->sc_hwsig; sig = old; uart_lock(sc->sc_hwmtx); - msr = uart_getreg(&sc->sc_bas, REG_MSR); + msr = uart_getreg(&sc->sc_bas, OCT_REG_MSR); uart_unlock(sc->sc_hwmtx); SIGCHG(msr & MSR_DSR, sig, SER_DSR, SER_DDSR); SIGCHG(msr & MSR_CTS, sig, SER_CTS, SER_DCTS); @@ -549,52 +546,57 @@ uart_lock(sc->sc_hwmtx); switch (request) { case UART_IOCTL_BREAK: - lcr = uart_getreg(bas, REG_LCR); + lcr = uart_getreg(bas, OCT_REG_LCR); if (data) - lcr |= LCR_SBREAK; + + lcr |= LCR_SBREAK; else lcr &= ~LCR_SBREAK; - uart_setreg(bas, REG_LCR, lcr); + uart_setreg(bas, OCT_REG_LCR, lcr); uart_barrier(bas); break; case UART_IOCTL_IFLOW: - lcr = uart_getreg(bas, REG_LCR); + lcr = uart_getreg(bas, OCT_REG_LCR); uart_barrier(bas); - uart_setreg(bas, REG_LCR, 0xbf); + /* What does EFR_ENABLE do?? RRS */ + uart_setreg(bas, OCT_REG_LCR, LCR_EFR_ENABLE); uart_barrier(bas); - efr = uart_getreg(bas, REG_EFR); + /* Don't know if this is correct ?? RRS */ + efr = uart_getreg(bas, OCT_REG_MCR); if (data) - efr |= EFR_RTS; + efr |= MCR_RTS; else - efr &= ~EFR_RTS; - uart_setreg(bas, REG_EFR, efr); + efr &= ~MCR_RTS; + uart_setreg(bas, OCT_REG_MCR, efr); uart_barrier(bas); - uart_setreg(bas, REG_LCR, lcr); + uart_setreg(bas, OCT_REG_LCR, lcr); uart_barrier(bas); break; case UART_IOCTL_OFLOW: - lcr = uart_getreg(bas, REG_LCR); + lcr = uart_getreg(bas, OCT_REG_LCR); uart_barrier(bas); - uart_setreg(bas, REG_LCR, 0xbf); + /* Don't know if this is correct ?? RRS */ + uart_setreg(bas, OCT_REG_LCR, LCR_EFR_ENABLE); uart_barrier(bas); - efr = uart_getreg(bas, REG_EFR); + /* Don't know if this is correct ?? RRS */ + efr = uart_getreg(bas, OCT_REG_MCR); if (data) - efr |= EFR_CTS; + efr |= MCR_DTR; else - efr &= ~EFR_CTS; - uart_setreg(bas, REG_EFR, efr); + efr &= ~MCR_DTR; + uart_setreg(bas, OCT_REG_MCR, efr); uart_barrier(bas); - uart_setreg(bas, REG_LCR, lcr); + uart_setreg(bas, OCT_REG_LCR, lcr); uart_barrier(bas); break; case UART_IOCTL_BAUD: - lcr = uart_getreg(bas, REG_LCR); - uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); + lcr = uart_getreg(bas, OCT_REG_LCR); + uart_setreg(bas, OCT_REG_LCR, lcr | LCR_DLAB); uart_barrier(bas); - divisor = uart_getreg(bas, REG_DLL) | - (uart_getreg(bas, REG_DLH) << 8); + divisor = uart_getreg(bas, OCT_REG_DLL) | + (uart_getreg(bas, OCT_REG_DLH) << 8); uart_barrier(bas); - uart_setreg(bas, REG_LCR, lcr); + uart_setreg(bas, OCT_REG_LCR, lcr); uart_barrier(bas); baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0; delay_changed = 1; @@ -622,11 +624,11 @@ bas = &sc->sc_bas; uart_lock(sc->sc_hwmtx); - iir = uart_getreg(bas, REG_IIR) & IIR_IMASK; + iir = uart_getreg(bas, OCT_REG_IIR) & IIR_IMASK; if (iir != IIR_NOPEND) { if (iir == IIR_RLS) { - lsr = uart_getreg(bas, REG_LSR); + lsr = uart_getreg(bas, OCT_REG_LSR); if (lsr & LSR_OE) ipend |= SER_INT_OVERRUN; if (lsr & LSR_BI) @@ -647,7 +649,7 @@ ipend |= SER_INT_SIGCHG; } else if (iir == IIR_BUSY) { - (void)uart_getreg(bas, REG_USR); + (void)uart_getreg(bas, OCT_REG_USR); } } uart_unlock(sc->sc_hwmtx); @@ -693,7 +695,7 @@ if (error) { return (error); } - uart_setreg(bas, REG_MCR, (MCR_DTR | MCR_RTS)); + uart_setreg(bas, OCT_REG_MCR, (MCR_DTR | MCR_RTS)); /* * Enable FIFOs. And check that the UART has them. If not, we're @@ -703,7 +705,7 @@ oct16550_drain(bas, UART_DRAIN_TRANSMITTER); #define ENABLE_OCTEON_FIFO 1 #ifdef ENABLE_OCTEON_FIFO - uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST); + uart_setreg(bas, OCT_REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST); #endif uart_barrier(bas); @@ -749,31 +751,31 @@ bas = &sc->sc_bas; uart_lock(sc->sc_hwmtx); - lsr = uart_getreg(bas, REG_LSR); + lsr = uart_getreg(bas, OCT_REG_LSR); while (lsr & LSR_RXRDY) { if (uart_rx_full(sc)) { sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; break; } - xc = uart_getreg(bas, REG_DATA); + xc = uart_getreg(bas, OCT_REG_RBR); if (lsr & LSR_FE) xc |= UART_STAT_FRAMERR; if (lsr & LSR_PE) xc |= UART_STAT_PARERR; uart_rx_put(sc, xc); - lsr = uart_getreg(bas, REG_LSR); + lsr = uart_getreg(bas, OCT_REG_LSR); } /* Discard everything left in the Rx FIFO. */ /* * First do a read/discard anyway, in case the UART was lying to us. * This was seen, when IIR said RBR, but LSR said no RXRDY */ - (void)uart_getreg(bas, REG_DATA); + (void)uart_getreg(bas, OCT_REG_RBR); while (lsr & LSR_RXRDY) { - (void)uart_getreg(bas, REG_DATA); + (void)uart_getreg(bas, OCT_REG_RBR); uart_barrier(bas); - lsr = uart_getreg(bas, REG_LSR); + lsr = uart_getreg(bas, OCT_REG_LSR); } uart_unlock(sc->sc_hwmtx); return (0); @@ -805,7 +807,7 @@ oct16550->mcr |= MCR_DTR; if (new & SER_RTS) oct16550->mcr |= MCR_RTS; - uart_setreg(bas, REG_MCR, oct16550->mcr); + uart_setreg(bas, OCT_REG_MCR, oct16550->mcr); uart_barrier(bas); uart_unlock(sc->sc_hwmtx); return (0); @@ -827,11 +829,11 @@ #else oct16550_wait_txhr_empty(bas, 100, oct16550_delay(bas)); - uart_setreg(bas, REG_IER, oct16550->ier | IER_ETXRDY); + uart_setreg(bas, OCT_REG_IER, oct16550->ier | IER_ETXRDY); uart_barrier(bas); for (i = 0; i < sc->sc_txdatasz; i++) { - uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]); + uart_setreg(bas, OCT_REG_THR, sc->sc_txbuf[i]); uart_barrier(bas); } sc->sc_txbusy = 1;
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