Date: Mon, 22 May 2006 14:33:22 -0400 From: "m m" <needacoder@gmail.com> To: "Chad Leigh -- Shire.Net LLC" <chad@shire.net> Cc: current@freebsd.org Subject: Re: FreeBSD is now self-hosting on the UltraSPARC T1 Message-ID: <1e4841eb0605221133s428d9136p3d5f7eff964167f4@mail.gmail.com> In-Reply-To: <FB03D201-4154-411E-AFE4-572CEBF76A92@shire.net> References: <1e4841eb0605211854i44c4aa4cm9dfc72506c2232ea@mail.gmail.com> <FB03D201-4154-411E-AFE4-572CEBF76A92@shire.net>
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On 5/22/06, Chad Leigh -- Shire.Net LLC <chad@shire.net> wrote: > > On May 21, 2006, at 7:54 PM, m m wrote: > > > While > > on topic, the Opterons aren't SMP either, and neither are the > > ht-Xeons... > > I would like t\o hear the rational for the Opterons (presumably the > dual core ones) not being SMP. They have two independent operating > cores in one physical package. Who cares how it is packaged? I > would tend to agree with you on the ht-Xeon in terms of general > descriptions. I do not know as well how the ht-xeon work as I don't > use any but it seems to me that the "SMP" moniker, at least in > FreeBSD, relate to how things are scheduled. SMP stands for "Symmetric MultiProcessing", which means that multiple processors have equal access latency to memory - typically accomplished by sitting the processors on a shared bus with memory. The MultiProcessor Opterons are _NOT_ SMP, they are _NUMA_ machines, "NonUniform Memory Access"; in the MP Opterons each processor has (or can have) its own "local" memory, which makes up only part of the shared address space. When an Opteron accesses an address that is not in its "local" memory, it has to talk to a remote processor's memory, thereby incurring a different access latency.
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