From owner-svn-src-all@freebsd.org Sat Dec 24 14:33:37 2016 Return-Path: Delivered-To: svn-src-all@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 3B12BC8E8F2; Sat, 24 Dec 2016 14:33:37 +0000 (UTC) (envelope-from avg@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 06ED0126D; Sat, 24 Dec 2016 14:33:36 +0000 (UTC) (envelope-from avg@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id uBOEXatm067155; Sat, 24 Dec 2016 14:33:36 GMT (envelope-from avg@FreeBSD.org) Received: (from avg@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id uBOEXZJh067151; Sat, 24 Dec 2016 14:33:35 GMT (envelope-from avg@FreeBSD.org) Message-Id: <201612241433.uBOEXZJh067151@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: avg set sender to avg@FreeBSD.org using -f From: Andriy Gapon Date: Sat, 24 Dec 2016 14:33:35 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-11@freebsd.org Subject: svn commit: r310517 - stable/11/sys/dev/ichiic X-SVN-Group: stable-11 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 24 Dec 2016 14:33:37 -0000 Author: avg Date: Sat Dec 24 14:33:35 2016 New Revision: 310517 URL: https://svnweb.freebsd.org/changeset/base/310517 Log: MFC r308219: ichiic/ig4: completely disengage from smbus Modified: stable/11/sys/dev/ichiic/ig4_iic.c stable/11/sys/dev/ichiic/ig4_pci.c stable/11/sys/dev/ichiic/ig4_reg.h stable/11/sys/dev/ichiic/ig4_var.h Directory Properties: stable/11/ (props changed) Modified: stable/11/sys/dev/ichiic/ig4_iic.c ============================================================================== --- stable/11/sys/dev/ichiic/ig4_iic.c Sat Dec 24 14:25:25 2016 (r310516) +++ stable/11/sys/dev/ichiic/ig4_iic.c Sat Dec 24 14:33:35 2016 (r310517) @@ -37,7 +37,7 @@ __FBSDID("$FreeBSD$"); /* - * Intel fourth generation mobile cpus integrated I2C device, smbus driver. + * Intel fourth generation mobile cpus integrated I2C deviceer. * * See ig4_reg.h for datasheet reference and notes. * See ig4_var.h for locking semantics. @@ -60,7 +60,6 @@ __FBSDID("$FreeBSD$"); #include #include -#include #include #include @@ -236,18 +235,13 @@ data_read(ig4iic_softc_t *sc) * the target address for when the controller later issues a START. */ static void -set_slave_addr(ig4iic_softc_t *sc, uint8_t slave, int trans_op) +set_slave_addr(ig4iic_softc_t *sc, uint8_t slave) { uint32_t tar; uint32_t ctl; int use_10bit; - use_10bit = sc->use_10bit; - if (trans_op & SMB_TRANS_7BIT) - use_10bit = 0; - if (trans_op & SMB_TRANS_10BIT) - use_10bit = 1; - + use_10bit = 0; if (sc->slave_valid && sc->last_slave == slave && sc->use_10bit == use_10bit) { return; @@ -291,208 +285,12 @@ set_slave_addr(ig4iic_softc_t *sc, uint8 } /* - * Issue START with byte command, possible count, and a variable length - * read or write buffer, then possible turn-around read. The read also - * has a possible count received. - * - * For SMBUS - - * - * Quick: START+ADDR+RD/WR STOP - * - * Normal: START+ADDR+WR CMD DATA..DATA STOP - * - * START+ADDR+RD CMD - * RESTART+ADDR RDATA..RDATA STOP - * (can also be used for I2C transactions) - * - * Process Call: START+ADDR+WR CMD DATAL DATAH - * RESTART+ADDR+RD RDATAL RDATAH STOP - * - * Block: START+ADDR+RD CMD - * RESTART+ADDR+RD RCOUNT DATA... STOP - * - * START+ADDR+WR CMD - * RESTART+ADDR+WR WCOUNT DATA... STOP - * - * For I2C - basically, no *COUNT fields, possibly no *CMD field. If the - * sender needs to issue a 2-byte command it will incorporate it - * into the write buffer and also set NOCMD. - * - * Generally speaking, the START+ADDR / RESTART+ADDR is handled automatically - * by the controller at the beginning of a command sequence or on a data - * direction turn-around, and we only need to tell it when to issue the STOP. - */ -static int -smb_transaction(ig4iic_softc_t *sc, char cmd, int op, - char *wbuf, int wcount, char *rbuf, int rcount, int *actualp) -{ - int error; - int unit; - uint32_t last; - - /* - * Debugging - dump registers - */ - if (ig4_dump) { - unit = device_get_unit(sc->dev); - if (ig4_dump & (1 << unit)) { - ig4_dump &= ~(1 << unit); - ig4iic_dump(sc); - } - } - - /* - * Issue START or RESTART with next data byte, clear any previous - * abort condition that may have been holding the txfifo in reset. - */ - last = IG4_DATA_RESTART; - reg_read(sc, IG4_REG_CLR_TX_ABORT); - if (actualp) - *actualp = 0; - - /* - * Issue command if not told otherwise (smbus). - */ - if ((op & SMB_TRANS_NOCMD) == 0) { - error = wait_status(sc, IG4_STATUS_TX_NOTFULL); - if (error) - goto done; - last |= (u_char)cmd; - if (wcount == 0 && rcount == 0 && (op & SMB_TRANS_NOSTOP) == 0) - last |= IG4_DATA_STOP; - reg_write(sc, IG4_REG_DATA_CMD, last); - last = 0; - } - - /* - * Clean out any previously received data. - */ - if (sc->rpos != sc->rnext && - (op & SMB_TRANS_NOREPORT) == 0) { - device_printf(sc->dev, - "discarding %d bytes of spurious data\n", - sc->rnext - sc->rpos); - } - sc->rpos = 0; - sc->rnext = 0; - - /* - * If writing and not told otherwise, issue the write count (smbus). - */ - if (wcount && (op & SMB_TRANS_NOCNT) == 0) { - error = wait_status(sc, IG4_STATUS_TX_NOTFULL); - if (error) - goto done; - last |= (u_char)cmd; - reg_write(sc, IG4_REG_DATA_CMD, last); - last = 0; - } - - /* - * Bulk write (i2c) - */ - while (wcount) { - error = wait_status(sc, IG4_STATUS_TX_NOTFULL); - if (error) - goto done; - last |= (u_char)*wbuf; - if (wcount == 1 && rcount == 0 && (op & SMB_TRANS_NOSTOP) == 0) - last |= IG4_DATA_STOP; - reg_write(sc, IG4_REG_DATA_CMD, last); - --wcount; - ++wbuf; - last = 0; - } - - /* - * Issue reads to xmit FIFO (strange, I know) to tell the controller - * to clock in data. At the moment just issue one read ahead to - * pipeline the incoming data. - * - * NOTE: In the case of NOCMD and wcount == 0 we still issue a - * RESTART here, even if the data direction has not changed - * from the previous CHAINing call. This we force the RESTART. - * (A new START is issued automatically by the controller in - * the other nominal cases such as a data direction change or - * a previous STOP was issued). - * - * If this will be the last byte read we must also issue the STOP - * at the end of the read. - */ - if (rcount) { - last = IG4_DATA_RESTART | IG4_DATA_COMMAND_RD; - if (rcount == 1 && - (op & (SMB_TRANS_NOSTOP | SMB_TRANS_NOCNT)) == - SMB_TRANS_NOCNT) { - last |= IG4_DATA_STOP; - } - reg_write(sc, IG4_REG_DATA_CMD, last); - last = IG4_DATA_COMMAND_RD; - } - - /* - * Bulk read (i2c) and count field handling (smbus) - */ - while (rcount) { - /* - * Maintain a pipeline by queueing the allowance for the next - * read before waiting for the current read. - */ - if (rcount > 1) { - if (op & SMB_TRANS_NOCNT) - last = (rcount == 2) ? IG4_DATA_STOP : 0; - else - last = 0; - reg_write(sc, IG4_REG_DATA_CMD, IG4_DATA_COMMAND_RD | - last); - } - error = wait_status(sc, IG4_STATUS_RX_NOTEMPTY); - if (error) { - if ((op & SMB_TRANS_NOREPORT) == 0) { - device_printf(sc->dev, - "rx timeout addr 0x%02x\n", - sc->last_slave); - } - goto done; - } - last = data_read(sc); - - if (op & SMB_TRANS_NOCNT) { - *rbuf = (u_char)last; - ++rbuf; - --rcount; - if (actualp) - ++*actualp; - } else { - /* - * Handle count field (smbus), which is not part of - * the rcount'ed buffer. The first read data in a - * bulk transfer is the count. - * - * XXX if rcount is loaded as 0 how do I generate a - * STOP now without issuing another RD or WR? - */ - if (rcount > (u_char)last) - rcount = (u_char)last; - op |= SMB_TRANS_NOCNT; - } - } - error = 0; -done: - /* XXX wait for xmit buffer to become empty */ - last = reg_read(sc, IG4_REG_TX_ABRT_SOURCE); - - return (error); -} - -/* * IICBUS API FUNCTIONS */ static int ig4iic_xfer_start(ig4iic_softc_t *sc, uint16_t slave) { - /* XXX 10-bit address support? */ - set_slave_addr(sc, slave >> 1, 0); + set_slave_addr(sc, slave >> 1); return (0); } @@ -706,7 +504,7 @@ ig4iic_reset(device_t dev, u_char speed, /* TODO handle speed configuration? */ if (oldaddr != NULL) *oldaddr = sc->last_slave << 1; - set_slave_addr(sc, addr >> 1, 0); + set_slave_addr(sc, addr >> 1); if (addr == IIC_UNKNOWN) sc->slave_valid = false; @@ -716,8 +514,6 @@ ig4iic_reset(device_t dev, u_char speed, } /* - * SMBUS API FUNCTIONS - * * Called from ig4iic_pci_attach/detach() */ int @@ -836,7 +632,6 @@ ig4iic_start(void *xdev) config_intrhook_disestablish(&sc->enum_hook); - /* Attach us to the smbus */ error = bus_generic_attach(sc->dev); if (error) { device_printf(sc->dev, @@ -844,8 +639,6 @@ ig4iic_start(void *xdev) } } - - int ig4iic_detach(ig4iic_softc_t *sc) { @@ -874,276 +667,6 @@ ig4iic_detach(ig4iic_softc_t *sc) return (0); } -int -ig4iic_smb_callback(device_t dev, int index, void *data) -{ - int error; - - switch (index) { - case SMB_REQUEST_BUS: - error = 0; - break; - case SMB_RELEASE_BUS: - error = 0; - break; - default: - error = SMB_EABORT; - break; - } - - return (error); -} - -/* - * Quick command. i.e. START + cmd + R/W + STOP and no data. It is - * unclear to me how I could implement this with the intel i2c controller - * because the controller sends STARTs and STOPs automatically with data. - */ -int -ig4iic_smb_quick(device_t dev, u_char slave, int how) -{ - - return (SMB_ENOTSUPP); -} - -/* - * Incremental send byte without stop (?). It is unclear why the slave - * address is specified if this presumably is used in combination with - * ig4iic_smb_quick(). - * - * (Also, how would this work anyway? Issue the last byte with writeb()?) - */ -int -ig4iic_smb_sendb(device_t dev, u_char slave, char byte) -{ - ig4iic_softc_t *sc = device_get_softc(dev); - uint32_t cmd; - int error; - - sx_xlock(&sc->call_lock); - mtx_lock(&sc->io_lock); - - set_slave_addr(sc, slave, 0); - cmd = byte; - if (wait_status(sc, IG4_STATUS_TX_NOTFULL) == 0) { - reg_write(sc, IG4_REG_DATA_CMD, cmd); - error = 0; - } else { - error = SMB_ETIMEOUT; - } - - mtx_unlock(&sc->io_lock); - sx_xunlock(&sc->call_lock); - return (error); -} - -/* - * Incremental receive byte without stop (?). It is unclear why the slave - * address is specified if this presumably is used in combination with - * ig4iic_smb_quick(). - */ -int -ig4iic_smb_recvb(device_t dev, u_char slave, char *byte) -{ - ig4iic_softc_t *sc = device_get_softc(dev); - int error; - - sx_xlock(&sc->call_lock); - mtx_lock(&sc->io_lock); - - set_slave_addr(sc, slave, 0); - reg_write(sc, IG4_REG_DATA_CMD, IG4_DATA_COMMAND_RD); - if (wait_status(sc, IG4_STATUS_RX_NOTEMPTY) == 0) { - *byte = data_read(sc); - error = 0; - } else { - *byte = 0; - error = SMB_ETIMEOUT; - } - - mtx_unlock(&sc->io_lock); - sx_xunlock(&sc->call_lock); - return (error); -} - -/* - * Write command and single byte in transaction. - */ -int -ig4iic_smb_writeb(device_t dev, u_char slave, char cmd, char byte) -{ - ig4iic_softc_t *sc = device_get_softc(dev); - int error; - - sx_xlock(&sc->call_lock); - mtx_lock(&sc->io_lock); - - set_slave_addr(sc, slave, 0); - error = smb_transaction(sc, cmd, SMB_TRANS_NOCNT, - &byte, 1, NULL, 0, NULL); - - mtx_unlock(&sc->io_lock); - sx_xunlock(&sc->call_lock); - return (error); -} - -/* - * Write command and single word in transaction. - */ -int -ig4iic_smb_writew(device_t dev, u_char slave, char cmd, short word) -{ - ig4iic_softc_t *sc = device_get_softc(dev); - char buf[2]; - int error; - - sx_xlock(&sc->call_lock); - mtx_lock(&sc->io_lock); - - set_slave_addr(sc, slave, 0); - buf[0] = word & 0xFF; - buf[1] = word >> 8; - error = smb_transaction(sc, cmd, SMB_TRANS_NOCNT, - buf, 2, NULL, 0, NULL); - - mtx_unlock(&sc->io_lock); - sx_xunlock(&sc->call_lock); - return (error); -} - -/* - * write command and read single byte in transaction. - */ -int -ig4iic_smb_readb(device_t dev, u_char slave, char cmd, char *byte) -{ - ig4iic_softc_t *sc = device_get_softc(dev); - int error; - - sx_xlock(&sc->call_lock); - mtx_lock(&sc->io_lock); - - set_slave_addr(sc, slave, 0); - error = smb_transaction(sc, cmd, SMB_TRANS_NOCNT, - NULL, 0, byte, 1, NULL); - - mtx_unlock(&sc->io_lock); - sx_xunlock(&sc->call_lock); - return (error); -} - -/* - * write command and read word in transaction. - */ -int -ig4iic_smb_readw(device_t dev, u_char slave, char cmd, short *word) -{ - ig4iic_softc_t *sc = device_get_softc(dev); - char buf[2]; - int error; - - sx_xlock(&sc->call_lock); - mtx_lock(&sc->io_lock); - - set_slave_addr(sc, slave, 0); - if ((error = smb_transaction(sc, cmd, SMB_TRANS_NOCNT, - NULL, 0, buf, 2, NULL)) == 0) { - *word = (u_char)buf[0] | ((u_char)buf[1] << 8); - } - - mtx_unlock(&sc->io_lock); - sx_xunlock(&sc->call_lock); - return (error); -} - -/* - * write command and word and read word in transaction - */ -int -ig4iic_smb_pcall(device_t dev, u_char slave, char cmd, - short sdata, short *rdata) -{ - ig4iic_softc_t *sc = device_get_softc(dev); - char rbuf[2]; - char wbuf[2]; - int error; - - sx_xlock(&sc->call_lock); - mtx_lock(&sc->io_lock); - - set_slave_addr(sc, slave, 0); - wbuf[0] = sdata & 0xFF; - wbuf[1] = sdata >> 8; - if ((error = smb_transaction(sc, cmd, SMB_TRANS_NOCNT, - wbuf, 2, rbuf, 2, NULL)) == 0) { - *rdata = (u_char)rbuf[0] | ((u_char)rbuf[1] << 8); - } - - mtx_unlock(&sc->io_lock); - sx_xunlock(&sc->call_lock); - return (error); -} - -int -ig4iic_smb_bwrite(device_t dev, u_char slave, char cmd, - u_char wcount, char *buf) -{ - ig4iic_softc_t *sc = device_get_softc(dev); - int error; - - sx_xlock(&sc->call_lock); - mtx_lock(&sc->io_lock); - - set_slave_addr(sc, slave, 0); - error = smb_transaction(sc, cmd, 0, - buf, wcount, NULL, 0, NULL); - - mtx_unlock(&sc->io_lock); - sx_xunlock(&sc->call_lock); - return (error); -} - -int -ig4iic_smb_bread(device_t dev, u_char slave, char cmd, - u_char *countp_char, char *buf) -{ - ig4iic_softc_t *sc = device_get_softc(dev); - int rcount = *countp_char; - int error; - - sx_xlock(&sc->call_lock); - mtx_lock(&sc->io_lock); - - set_slave_addr(sc, slave, 0); - error = smb_transaction(sc, cmd, 0, - NULL, 0, buf, rcount, &rcount); - *countp_char = rcount; - - mtx_unlock(&sc->io_lock); - sx_xunlock(&sc->call_lock); - return (error); -} - -int -ig4iic_smb_trans(device_t dev, int slave, char cmd, int op, - char *wbuf, int wcount, char *rbuf, int rcount, - int *actualp) -{ - ig4iic_softc_t *sc = device_get_softc(dev); - int error; - - sx_xlock(&sc->call_lock); - mtx_lock(&sc->io_lock); - - set_slave_addr(sc, slave, op); - error = smb_transaction(sc, cmd, op, - wbuf, wcount, rbuf, rcount, actualp); - - mtx_unlock(&sc->io_lock); - sx_xunlock(&sc->call_lock); - return (error); -} - /* * Interrupt Operation, see ig4_var.h for locking semantics. */ Modified: stable/11/sys/dev/ichiic/ig4_pci.c ============================================================================== --- stable/11/sys/dev/ichiic/ig4_pci.c Sat Dec 24 14:25:25 2016 (r310516) +++ stable/11/sys/dev/ichiic/ig4_pci.c Sat Dec 24 14:33:35 2016 (r310517) @@ -37,7 +37,7 @@ __FBSDID("$FreeBSD$"); /* - * Intel fourth generation mobile cpus integrated I2C device, smbus driver. + * Intel fourth generation mobile cpus integrated I2C device. * * See ig4_reg.h for datasheet reference and notes. */ @@ -59,11 +59,8 @@ __FBSDID("$FreeBSD$"); #include #include -#include #include -#include "smbus_if.h" - #include #include @@ -167,20 +164,6 @@ static device_method_t ig4iic_pci_method DEVMETHOD(device_attach, ig4iic_pci_attach), DEVMETHOD(device_detach, ig4iic_pci_detach), - /* SMBus methods from ig4_smb.c */ - DEVMETHOD(smbus_callback, ig4iic_smb_callback), - DEVMETHOD(smbus_quick, ig4iic_smb_quick), - DEVMETHOD(smbus_sendb, ig4iic_smb_sendb), - DEVMETHOD(smbus_recvb, ig4iic_smb_recvb), - DEVMETHOD(smbus_writeb, ig4iic_smb_writeb), - DEVMETHOD(smbus_writew, ig4iic_smb_writew), - DEVMETHOD(smbus_readb, ig4iic_smb_readb), - DEVMETHOD(smbus_readw, ig4iic_smb_readw), - DEVMETHOD(smbus_pcall, ig4iic_smb_pcall), - DEVMETHOD(smbus_bwrite, ig4iic_smb_bwrite), - DEVMETHOD(smbus_bread, ig4iic_smb_bread), - DEVMETHOD(smbus_trans, ig4iic_smb_trans), - DEVMETHOD(iicbus_transfer, ig4iic_transfer), DEVMETHOD(iicbus_reset, ig4iic_reset), DEVMETHOD(iicbus_callback, iicbus_null_callback), @@ -199,6 +182,5 @@ static devclass_t ig4iic_pci_devclass; DRIVER_MODULE_ORDERED(ig4iic, pci, ig4iic_pci_driver, ig4iic_pci_devclass, 0, 0, SI_ORDER_ANY); MODULE_DEPEND(ig4iic, pci, 1, 1, 1); -MODULE_DEPEND(ig4iic, smbus, SMBUS_MINVER, SMBUS_PREFVER, SMBUS_MAXVER); MODULE_DEPEND(ig4iic, iicbus, IICBUS_MINVER, IICBUS_PREFVER, IICBUS_MAXVER); MODULE_VERSION(ig4iic, 1); Modified: stable/11/sys/dev/ichiic/ig4_reg.h ============================================================================== --- stable/11/sys/dev/ichiic/ig4_reg.h Sat Dec 24 14:25:25 2016 (r310516) +++ stable/11/sys/dev/ichiic/ig4_reg.h Sat Dec 24 14:33:35 2016 (r310517) @@ -47,14 +47,14 @@ * I am also using the linux driver code as a reference to help resolve any * issues that come. These will be specifically documented in the code. * - * Please see protocol notes in section 5.21. This controller is an I2C - * master only and cannot act as a slave. The IO voltage should be set by - * the BIOS. Standard (100Kb/s) and Fast (400Kb/s) and fast mode plus - * (1MB/s) is supported. High speed mode (3.4 MB/s) is NOT supported. + * This controller is an I2C master only and cannot act as a slave. The IO + * voltage should be set by the BIOS. Standard (100Kb/s) and Fast (400Kb/s) + * and fast mode plus (1MB/s) is supported. High speed mode (3.4 MB/s) is NOT + * supported. */ -#ifndef _BUS_SMBUS_INTELGEN4_IG4_REG_H_ -#define _BUS_SMBUS_INTELGEN4_IG4_REG_H_ +#ifndef _ICHIIC_IG4_REG_H_ +#define _ICHIIC_IG4_REG_H_ /* * 22.2 MMIO registers can be accessed through BAR0 in PCI mode or through @@ -619,4 +619,4 @@ #define IG4_SWLTR_SNOOP_VALUE_DECODE(v) ((v) & 0x3F) #define IG4_SWLTR_SNOOP_VALUE_ENCODE(v) ((v) & 0x3F) -#endif +#endif /* _ICHIIC_IG4_REG_H_ */ Modified: stable/11/sys/dev/ichiic/ig4_var.h ============================================================================== --- stable/11/sys/dev/ichiic/ig4_var.h Sat Dec 24 14:25:25 2016 (r310516) +++ stable/11/sys/dev/ichiic/ig4_var.h Sat Dec 24 14:33:35 2016 (r310517) @@ -35,13 +35,12 @@ * $FreeBSD$ */ -#ifndef _BUS_SMBUS_INTELGEN4_IG4_VAR_H_ -#define _BUS_SMBUS_INTELGEN4_IG4_VAR_H_ +#ifndef _ICHIIC_IG4_VAR_H_ +#define _ICHIIC_IG4_VAR_H_ #include "bus_if.h" #include "device_if.h" #include "pci_if.h" -#include "smbus_if.h" #include "iicbus_if.h" #define IG4_RBUFSIZE 128 @@ -75,12 +74,12 @@ struct ig4iic_softc { /* * Locking semantics: * - * Functions implementing the smbus interface that interact + * Functions implementing the icbus interface that interact * with the controller acquire an exclusive lock on call_lock * to prevent interleaving of calls to the interface and a lock on * io_lock right afterwards, to synchronize controller I/O activity. - * - * The interrupt handler can only read data while no ig4iic_smb_* call + * + * The interrupt handler can only read data while no iicbus call * is in progress or while io_lock is dropped during mtx_sleep in * wait_status and set_controller. It is safe to drop io_lock in those * places, because the interrupt handler only accesses those registers: @@ -91,7 +90,7 @@ struct ig4iic_softc { * * Locking outside of those places is required to make the content * of rpos/rnext predictable (e.g. whenever data_read is called and in - * smb_transaction). + * ig4iic_transfer). */ struct sx call_lock; struct mtx io_lock; @@ -103,20 +102,8 @@ typedef struct ig4iic_softc ig4iic_softc int ig4iic_attach(ig4iic_softc_t *sc); int ig4iic_detach(ig4iic_softc_t *sc); -/* SMBus methods */ -extern smbus_callback_t ig4iic_smb_callback; -extern smbus_quick_t ig4iic_smb_quick; -extern smbus_sendb_t ig4iic_smb_sendb; -extern smbus_recvb_t ig4iic_smb_recvb; -extern smbus_writeb_t ig4iic_smb_writeb; -extern smbus_writew_t ig4iic_smb_writew; -extern smbus_readb_t ig4iic_smb_readb; -extern smbus_readw_t ig4iic_smb_readw; -extern smbus_pcall_t ig4iic_smb_pcall; -extern smbus_bwrite_t ig4iic_smb_bwrite; -extern smbus_bread_t ig4iic_smb_bread; -extern smbus_trans_t ig4iic_smb_trans; +/* iicbus methods */ extern iicbus_transfer_t ig4iic_transfer; extern iicbus_reset_t ig4iic_reset; -#endif +#endif /* _ICHIIC_IG4_VAR_H_ */