From owner-svn-src-stable-10@FreeBSD.ORG Tue Oct 21 01:48:20 2014 Return-Path: Delivered-To: svn-src-stable-10@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [8.8.178.115]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id 32CF5357; Tue, 21 Oct 2014 01:48:20 +0000 (UTC) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 04C37A39; Tue, 21 Oct 2014 01:48:20 +0000 (UTC) Received: from svn.freebsd.org ([127.0.1.70]) by svn.freebsd.org (8.14.9/8.14.9) with ESMTP id s9L1mJR0035616; Tue, 21 Oct 2014 01:48:19 GMT (envelope-from yongari@FreeBSD.org) Received: (from yongari@localhost) by svn.freebsd.org (8.14.9/8.14.9/Submit) id s9L1mJ0d035615; Tue, 21 Oct 2014 01:48:19 GMT (envelope-from yongari@FreeBSD.org) Message-Id: <201410210148.s9L1mJ0d035615@svn.freebsd.org> X-Authentication-Warning: svn.freebsd.org: yongari set sender to yongari@FreeBSD.org using -f From: Pyun YongHyeon Date: Tue, 21 Oct 2014 01:48:19 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-10@freebsd.org Subject: svn commit: r273361 - stable/10/sys/dev/pci X-SVN-Group: stable-10 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-stable-10@freebsd.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: SVN commit messages for only the 10-stable src tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 21 Oct 2014 01:48:20 -0000 Author: yongari Date: Tue Oct 21 01:48:19 2014 New Revision: 273361 URL: https://svnweb.freebsd.org/changeset/base/273361 Log: MFC r272729,272732: Add new quirk PCI_QUIRK_MSI_INTX_BUG to pci(4). QAC AR816x/E2200 controller has a silicon bug that MSI interrupt does not assert if PCIM_CMD_INTxDIS bit of command register is set. Modified: stable/10/sys/dev/pci/pci.c Directory Properties: stable/10/ (props changed) Modified: stable/10/sys/dev/pci/pci.c ============================================================================== --- stable/10/sys/dev/pci/pci.c Tue Oct 21 01:34:18 2014 (r273360) +++ stable/10/sys/dev/pci/pci.c Tue Oct 21 01:48:19 2014 (r273361) @@ -196,6 +196,7 @@ struct pci_quirk { #define PCI_QUIRK_ENABLE_MSI_VM 3 /* Older chipset in VM where MSI works */ #define PCI_QUIRK_UNMAP_REG 4 /* Ignore PCI map register */ #define PCI_QUIRK_DISABLE_MSIX 5 /* MSI-X doesn't work */ +#define PCI_QUIRK_MSI_INTX_BUG 6 /* PCIM_CMD_INTxDIS disables MSI */ int arg1; int arg2; }; @@ -255,6 +256,15 @@ static const struct pci_quirk pci_quirks */ { 0x43851002, PCI_QUIRK_UNMAP_REG, 0x14, 0 }, + /* + * Atheros AR8161/AR8162/E2200 ethernet controller has a bug that + * MSI interrupt does not assert if PCIM_CMD_INTxDIS bit of the + * command register is set. + */ + { 0x10911969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, + { 0xE0911969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, + { 0x10901969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, + { 0 } }; @@ -3624,8 +3634,14 @@ pci_setup_intr(device_t dev, device_t ch mte->mte_handlers++; } - /* Make sure that INTx is disabled if we are using MSI/MSIX */ - pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS); + if (!pci_has_quirk(pci_get_devid(dev), + PCI_QUIRK_MSI_INTX_BUG)) { + /* + * Make sure that INTx is disabled if we are + * using MSI/MSIX + */ + pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS); + } bad: if (error) { (void)bus_generic_teardown_intr(dev, child, irq,