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From: Dmitry Marakasov <amdmi3@FreeBSD.org>
Date: Fri, 19 Oct 2018 09:30:11 +0000 (UTC)
To: ports-committers@freebsd.org, svn-ports-all@freebsd.org,
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Subject: svn commit: r482419 - head/cad/verilog-mode.el
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Author: amdmi3
Date: Fri Oct 19 09:30:10 2018
New Revision: 482419
URL: https://svnweb.freebsd.org/changeset/ports/482419

Log:
  - Update WWW
  
  Approved by:	portmgr blanket

Modified:
  head/cad/verilog-mode.el/pkg-descr

Modified: head/cad/verilog-mode.el/pkg-descr
==============================================================================
--- head/cad/verilog-mode.el/pkg-descr	Fri Oct 19 09:06:29 2018	(r482418)
+++ head/cad/verilog-mode.el/pkg-descr	Fri Oct 19 09:30:10 2018	(r482419)
@@ -6,4 +6,4 @@ Recent versions allow you to insert AUTOS in non-AUTO 
 interconnect can be easily modified. You can also expand Verilog-2001 ".*"
 instantiations, to see what ports will be connected by simulators.
 
-WWW: http://www.veripool.org/wiki/verilog-mode
+WWW: https://www.veripool.org/wiki/verilog-mode