From owner-svn-src-head@FreeBSD.ORG Mon Feb 24 04:48:46 2014 Return-Path: Delivered-To: svn-src-head@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id D3CABD06; Mon, 24 Feb 2014 04:48:46 +0000 (UTC) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.freebsd.org (Postfix) with ESMTPS id A3B181FF4; Mon, 24 Feb 2014 04:48:46 +0000 (UTC) Received: from svn.freebsd.org ([127.0.1.70]) by svn.freebsd.org (8.14.8/8.14.8) with ESMTP id s1O4mkKq017617; Mon, 24 Feb 2014 04:48:46 GMT (envelope-from adrian@svn.freebsd.org) Received: (from adrian@localhost) by svn.freebsd.org (8.14.8/8.14.8/Submit) id s1O4mk0Z017616; Mon, 24 Feb 2014 04:48:46 GMT (envelope-from adrian@svn.freebsd.org) Message-Id: <201402240448.s1O4mk0Z017616@svn.freebsd.org> From: Adrian Chadd Date: Mon, 24 Feb 2014 04:48:46 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r262432 - head/sys/mips/conf X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.17 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 24 Feb 2014 04:48:46 -0000 Author: adrian Date: Mon Feb 24 04:48:46 2014 New Revision: 262432 URL: http://svnweb.freebsd.org/changeset/base/262432 Log: Add the AR8327 bits to the DB120 config file. There's plenty of hints that I haven't yet fleshed out and are hardcoded in arswitch_8327.c. They're listed here (from OpenWRT) for completeness. This is enough to get the thing up, running and pinging. Note that the mdiobus for the on-switch switch changes - the AR8327 probes first, which exposes mdio1, and thus the arge1 mdiobus will probe and attach as mdio2. That is what the AR9344 on-chip switch has to attach to. Tested: * Qualcomm Atheros DB120 Modified: head/sys/mips/conf/DB120.hints Modified: head/sys/mips/conf/DB120.hints ============================================================================== --- head/sys/mips/conf/DB120.hints Mon Feb 24 04:47:27 2014 (r262431) +++ head/sys/mips/conf/DB120.hints Mon Feb 24 04:48:46 2014 (r262432) @@ -14,13 +14,37 @@ hint.argemdio.0.order=0 hint.ar934x_gmac.0.gmac_cfg=0x41 # GMAC0 here - connected to an AR8327 -#hint.arswitch.0.at="mdio0" -#hint.arswitch.0.is_7240=0 -#hint.arswitch.0.is_9340=0 # not the internal switch! -#hint.arswitch.0.numphys=5 -#hint.arswitch.0.phy4cpu=0 -#hint.arswitch.0.is_rgmii=1 -#hint.arswitch.0.is_gmii=0 +hint.arswitch.0.at="mdio0" +hint.arswitch.0.is_7240=0 +hint.arswitch.0.is_9340=0 # not the internal switch! +hint.arswitch.0.numphys=5 +hint.arswitch.0.phy4cpu=0 +hint.arswitch.0.is_rgmii=1 +hint.arswitch.0.is_gmii=0 +# XXX other AR8327 configuration parameters + +# pad0 cfg: +# .mode = AR8327_PAD_MAC_RGMII, +# .txclk_delay_en = true, +# .rxclk_delay_en = true, +# .txclk_delay_sel = AR8327_CLK_DELAY_SEL1, +# .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2, + +# .led_ctrl0 = 0x00000000, +# .led_ctrl1 = 0xc737c737, +# .led_ctrl2 = 0x00000000, +# .led_ctrl3 = 0x00c30c00, +# .open_drain = true, + +# .port0_cfg = { +# .force_link = 1, +# .speed = AR8327_PORT_SPEED_1000, +# .duplex = 1, +# .txpause = 1, +# .rxpause = 1, +# }, + +# port6 cfg? # XXX OpenWRT DB120 BSP doesn't have media/duplex set? hint.arge.0.phymask=0x0 @@ -36,7 +60,9 @@ hint.argemdio.1.msize=0x1000 hint.argemdio.1.order=0 # Embedded switch on the AR9344 -hint.arswitch.1.at="mdio1" +# mdio1 is actually created as the AR8327 internal bus; so +# this pops up as mdio2. +hint.arswitch.1.at="mdio2" hint.arswitch.1.is_7240=0 hint.arswitch.1.is_9340=1 hint.arswitch.1.numphys=4