From owner-svn-src-all@freebsd.org Fri Jun 19 18:40:40 2020 Return-Path: Delivered-To: svn-src-all@mailman.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.nyi.freebsd.org (Postfix) with ESMTP id 0E6FB335F3C; Fri, 19 Jun 2020 18:40:40 +0000 (UTC) (envelope-from bdragon@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 49pSKz6j7qz4dhC; Fri, 19 Jun 2020 18:40:39 +0000 (UTC) (envelope-from bdragon@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id C8F571F8E3; Fri, 19 Jun 2020 18:40:39 +0000 (UTC) (envelope-from bdragon@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id 05JIedWs068866; Fri, 19 Jun 2020 18:40:39 GMT (envelope-from bdragon@FreeBSD.org) Received: (from bdragon@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id 05JIedq8068864; Fri, 19 Jun 2020 18:40:39 GMT (envelope-from bdragon@FreeBSD.org) Message-Id: <202006191840.05JIedq8068864@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: bdragon set sender to bdragon@FreeBSD.org using -f From: Brandon Bergren Date: Fri, 19 Jun 2020 18:40:39 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r362407 - in head/sys/powerpc: booke include X-SVN-Group: head X-SVN-Commit-Author: bdragon X-SVN-Commit-Paths: in head/sys/powerpc: booke include X-SVN-Commit-Revision: 362407 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.33 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 19 Jun 2020 18:40:40 -0000 Author: bdragon Date: Fri Jun 19 18:40:39 2020 New Revision: 362407 URL: https://svnweb.freebsd.org/changeset/base/362407 Log: [PowerPC] Fix booke64 qemu infinite loop in L2 cache enable Since qemu does not implement the L2 cache, we get stuck forever waiting for a bit to be set when trying to invalidate it. To prevent that, we should bail out if the L2 cache is missing. One easy way to check this is L2CFG0 == 0 (since L2CSIZE always has at least one bit set in a valid implementation) (tested on qemu, rb800, and x5000) Reviewed by: jhibbits Sponsored by: Tag1 Consulting, Inc. Differential Revision: https://reviews.freebsd.org/D25225 Modified: head/sys/powerpc/booke/machdep_e500.c head/sys/powerpc/include/spr.h Modified: head/sys/powerpc/booke/machdep_e500.c ============================================================================== --- head/sys/powerpc/booke/machdep_e500.c Fri Jun 19 18:36:10 2020 (r362406) +++ head/sys/powerpc/booke/machdep_e500.c Fri Jun 19 18:40:39 2020 (r362407) @@ -91,7 +91,17 @@ booke_enable_l2_cache(void) if ((((mfpvr() >> 16) & 0xFFFF) == FSL_E500mc) || (((mfpvr() >> 16) & 0xFFFF) == FSL_E5500)) { csr = mfspr(SPR_L2CSR0); - if ((csr & L2CSR0_L2E) == 0) { + /* + * Don't actually attempt to manipulate the L2 cache if + * L2CFG0 is zero. + * + * Any chip with a working L2 cache will have a nonzero + * L2CFG0, as it will have a nonzero L2CSIZE field. + * + * This fixes waiting forever for cache enable in qemu, + * which does not implement the L2 cache. + */ + if (mfspr(SPR_L2CFG0) != 0 && (csr & L2CSR0_L2E) == 0) { l2cache_inval(); l2cache_enable(); } Modified: head/sys/powerpc/include/spr.h ============================================================================== --- head/sys/powerpc/include/spr.h Fri Jun 19 18:36:10 2020 (r362406) +++ head/sys/powerpc/include/spr.h Fri Jun 19 18:40:39 2020 (r362407) @@ -887,6 +887,7 @@ #define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */ #define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */ +#define SPR_L2CFG0 0x207 /* ..8 L2 Configuration Register 0 */ #define SPR_L2CSR0 0x3F9 /* ..8 L2 Cache Control and Status Register 0 */ #define L2CSR0_L2E 0x80000000 /* L2 Cache Enable */ #define L2CSR0_L2PE 0x40000000 /* L2 Cache Parity Enable */