From owner-svn-src-all@FreeBSD.ORG Mon Jun 4 14:27:54 2012 Return-Path: Delivered-To: svn-src-all@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 9D635106564A; Mon, 4 Jun 2012 14:27:54 +0000 (UTC) (envelope-from kostikbel@gmail.com) Received: from mail.zoral.com.ua (mx0.zoral.com.ua [91.193.166.200]) by mx1.freebsd.org (Postfix) with ESMTP id 330D08FC18; Mon, 4 Jun 2012 14:27:54 +0000 (UTC) Received: from skuns.kiev.zoral.com.ua (localhost [127.0.0.1]) by mail.zoral.com.ua (8.14.2/8.14.2) with ESMTP id q54ERoGK011115; Mon, 4 Jun 2012 17:27:50 +0300 (EEST) (envelope-from kostikbel@gmail.com) Received: from deviant.kiev.zoral.com.ua (kostik@localhost [127.0.0.1]) by deviant.kiev.zoral.com.ua (8.14.5/8.14.5) with ESMTP id q54ERnu1091772; Mon, 4 Jun 2012 17:27:49 +0300 (EEST) (envelope-from kostikbel@gmail.com) Received: (from kostik@localhost) by deviant.kiev.zoral.com.ua (8.14.5/8.14.5/Submit) id q54ERnho091771; Mon, 4 Jun 2012 17:27:49 +0300 (EEST) (envelope-from kostikbel@gmail.com) X-Authentication-Warning: deviant.kiev.zoral.com.ua: kostik set sender to kostikbel@gmail.com using -f Date: Mon, 4 Jun 2012 17:27:49 +0300 From: Konstantin Belousov To: Attilio Rao Message-ID: <20120604142749.GB85127@deviant.kiev.zoral.com.ua> References: <201206021810.q52IAGZA004238@svn.freebsd.org> <4FCC873B.90104@freebsd.org> <20120604125050.GA85127@deviant.kiev.zoral.com.ua> Mime-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="OwLcNYc0lM97+oe1" Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.4.2.3i X-Virus-Scanned: clamav-milter 0.95.2 at skuns.kiev.zoral.com.ua X-Virus-Status: Clean X-Spam-Status: No, score=-4.0 required=5.0 tests=ALL_TRUSTED,AWL,BAYES_00 autolearn=ham version=3.2.5 X-Spam-Checker-Version: SpamAssassin 3.2.5 (2008-06-10) on skuns.kiev.zoral.com.ua Cc: svn-src-head@freebsd.org, Tijl Coosemans , src-committers@freebsd.org, svn-src-all@freebsd.org Subject: Re: svn commit: r236456 - in head/sys: amd64/include i386/include X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 04 Jun 2012 14:27:54 -0000 --OwLcNYc0lM97+oe1 Content-Type: text/plain; charset=koi8-r Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Mon, Jun 04, 2012 at 02:58:57PM +0100, Attilio Rao wrote: > 2012/6/4 Konstantin Belousov : > > On Mon, Jun 04, 2012 at 12:00:27PM +0200, Tijl Coosemans wrote: > >> On 02-06-2012 20:10, Konstantin Belousov wrote: > >> > Author: kib > >> > Date: Sat Jun =9A2 18:10:16 2012 > >> > New Revision: 236456 > >> > URL: http://svn.freebsd.org/changeset/base/236456 > >> > > >> > Log: > >> > =9A Use plain store for atomic_store_rel on x86, instead of implicit= ly > >> > =9A locked xchg instruction. =9AIA32 memory model guarantees that st= ore has > >> > =9A release semantic, since stores cannot pass loads or stores. > >> > >> They can pass non-temporal stores can't they? > > Sure. But (our) barriers only work for WB memory accesses, in respect t= o other > > WB memory accesses. > > > > The atomic(9) contains not quite explicit mention of the requirement, > > for ia32 and more direct notion for ia64. It could probably be reworded= to > > mention memory access type explicitely for ia32 too. >=20 > I don't think this is right. > What if I want to use NTI in a block of code locked? What if I want to > use CLFLUSH? I simply cannot do that now because of the reordering > requirement. Assuming that NTI means "Non Temporal Instruction", Intel explicit requirement is to use fence barrier if order shall be ensured. This, as well as CLFLUSH use, is somewhat commonly documented. More, CLFLUSH is documented by Intel to _not_ serialize with any other fencing or serialization instruction, except MFENCE. So xchg-based _store_rel is not different from mov-based _store_rel for CLFLUSH and non-temporal ops. I do not see how you note is relevant. > Also, there is the more worrisome case of the string operations. If > gcc/clang optimize the code in order to do string operations between > locked path, this is not valid anymore as they can be reordered > against the _rel() barrier. They cannot. Fast string operation volatile store order only among string operation itself, the operation cannot pass sequential store. The store used in _store_rel thus cannot be passed by fast string optimizations. I do not see how you note is relevant there, again. >=20 > However, we should consider atomic(9) as a script for MI requirement > of our locking primitives among the architectures. Right now too many > things live on assumptions of people doing patches (like this case) > rather than actually working on a common policy of what we can easilly > support and what we can't. >=20 > I also wondered often if we should use *fence on architectures > supporting them, by default, because of the possibility to use FPU now > (which wasn't present back in the day) and thus we cannot really > guarantee memory ordering over stores of memory areas bigger than a > quad-word. If we don't want to add the burden, we should explicitely > mention that in atomic(9) or any other place. The proposal to use fence explicitely contradicts recommendations from the AMD Optimization Guide, which, JFYI, I cited in the updated comment in the patch. How is FPU relevant to the memory model discussion, I left out of the answer. >=20 > Definitively: I think this patch violates some edge cases. Please back it= out. No. I explicitely inform you that I consider the backout request as frivolous, technically unfounded, and that I will not back it out. --OwLcNYc0lM97+oe1 Content-Type: application/pgp-signature Content-Disposition: inline -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (FreeBSD) iEYEARECAAYFAk/MxeUACgkQC3+MBN1Mb4hpagCfSnSKT0ZdhVH3/wUvvdBe5TCH CeQAmwY/wASzpG9nu7uOB9GbxPywH9pb =GTZq -----END PGP SIGNATURE----- --OwLcNYc0lM97+oe1--