Date: Fri, 10 Jun 2022 13:06:30 +0000 From: bugzilla-noreply@freebsd.org To: toolchain@FreeBSD.org Subject: [Bug 264590] assembler generates wrong opcodes of instructions fdiv fdivp fdivr fdivrp fsub fsubp fsubr fsubrp Message-ID: <bug-264590-29464-V2BCKa61eC@https.bugs.freebsd.org/bugzilla/> In-Reply-To: <bug-264590-29464@https.bugs.freebsd.org/bugzilla/> References: <bug-264590-29464@https.bugs.freebsd.org/bugzilla/>
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https://bugs.freebsd.org/bugzilla/show_bug.cgi?id=3D264590 --- Comment #3 from var@schellong.biz --- Intel: FDIV ST(0), ST(i) D8 F0+i Divide ST(0) by ST(i) and store result in ST(0= ). FDIV ST(i), ST(0) DC F8+i Divide ST(i) by ST(0) and store result in ST(i= ). FDIVP ST(i), ST(0) DE F8+i Divide ST(i) by ST(0), store result in ST(i), = and pop the register stack. FDIVP DE F9 Divide ST(1) by ST(0), store result in ST(1), = and pop the register stack. FDIVRP DE F1 Divide ST(0) by ST(1), store result in ST(1), = and pop the register stack. AMD: FDIV ST(0), ST(i) D8 F0+i Replace ST(0) with ST(0)/ST(i). FDIV ST(i), ST(0) DC F8+i Replace ST(i) with ST(i)/ST(0). FDIVP ST(i), ST(0) DE F8+i Replace ST(i) with ST(i)/ST(0), and pop the x87 register stack. FDIVP DE F9 Replace ST(1) with ST(1)/ST(0), and pop the x87 register stack. My opcodes 'DE F9' and 'DE F1' are correct. --=20 You are receiving this mail because: You are the assignee for the bug.=
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