Date: Sun, 7 Apr 2002 18:31:33 -0700 (PDT) From: Jake Burkholder <jake@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 9348 for review Message-ID: <200204080131.g381VXo36788@freefall.freebsd.org>
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http://people.freebsd.org/~peter/p4db/chv.cgi?CH=9348 Change 9348 by jake@jake_sparc64 on 2002/04/07 18:31:21 Implement console support; works pretty well, seems to drop output characters sometimes, input works for ddb. Affected files ... ... //depot/projects/sparc64/sys/dev/se/se_console.c#2 edit ... //depot/projects/sparc64/sys/dev/se/sereg.h#4 edit Differences ... ==== //depot/projects/sparc64/sys/dev/se/se_console.c#2 (text+ko) ==== @@ -1,3 +1,31 @@ +/*- + * Copyright (c) 2002 Jake Burkholder. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + #include <sys/param.h> #include <sys/kernel.h> #include <sys/systm.h> @@ -10,6 +38,9 @@ #include <machine/bus.h> #include <sys/rman.h> #include <sys/tty.h> +#include <sys/ktr.h> + +#ifdef __sparc64__ #include <ofw/openfirm.h> #include <ofw/ofw_pci.h> @@ -21,14 +52,21 @@ #include <sparc64/isa/ofw_isa.h> #include <sparc64/ebus/ebusvar.h> -#define CDEV_MAJOR 0 +#include <dev/se/sereg.h> + +#define SE_CNREAD_1(off) \ + bus_space_read_1(&se_cntag, se_cnhandle, se_cnchan + (off)) +#define SE_CNWRITE_1(off, val) \ + bus_space_write_1(&se_cntag, se_cnhandle, se_cnchan + (off), (val)) #define SE_CONSOLE(flags) ((flags) & 0x10) #define SE_FORCECONSOLE(flags) ((flags) & 0x20) -devclass_t se_devclass; +#define SE_CHANNELS 2 + +#define KTR_SE KTR_CT4 -#define SE_UNITS 2 +#define CDEV_MAJOR 200 static cn_probe_t se_cnprobe; static cn_init_t se_cninit; @@ -36,36 +74,40 @@ static cn_checkc_t se_cncheckc; static cn_putc_t se_cnputc; -static struct bus_space_tag cn_bustag; -static bus_space_handle_t cn_bushandle; -static bus_addr_t cn_phys; +static void se_cnregdump(void); + +static u_char se_cnchan; +static struct bus_space_tag se_cntag; +static bus_space_handle_t se_cnhandle; CONS_DRIVER(se, se_cnprobe, se_cninit, NULL, se_cngetc, se_cncheckc, se_cnputc, NULL); -static phandle_t -OF_traverse(phandle_t root, int (*func)(phandle_t)) +static int +OF_traverse(phandle_t root, phandle_t *node, + int (*func)(phandle_t, phandle_t *)) { - phandle_t node; - phandle_t rv; + phandle_t child; - for (node = OF_child(root); node != 0; node = OF_peer(node)) { - if ((rv = func(node)) > 0 || - (rv = OF_traverse(node, func)) > 0) - return (rv); + for (child = OF_child(root); child != 0; child = OF_peer(child)) { + if (func(child, node) == 0 || + OF_traverse(child, node, func) == 0) + return (0); } return (-1); } static int -se_cnfind(phandle_t node) +se_cnfind(phandle_t child, phandle_t *node) { char name[8]; - if (OF_getprop(node, "name", name, sizeof(name)) < 0 || - strncmp(name, "se", sizeof(name)) != 0) - return (-1); - return (node); + if (OF_getprop(child, "name", name, sizeof(name)) != -1 && + strncmp(name, "se", sizeof(name)) == 0) { + *node = child; + return (0); + } + return (-1); } static int @@ -88,8 +130,9 @@ int i; if (OF_getprop(node, "reg", ®, sizeof(reg)) == -1 || - (rsz = OF_getprop(parent, "ranges", ir, sizeof(ir))) == -1) + (rsz = OF_getprop(parent, "ranges", ir, sizeof(ir))) == -1) { return (ENXIO); + } phys = ISA_REG_PHYS(®); dummy = phys + 8; type = ofw_isa_map_iorange(ir, rsz / sizeof(*ir), &phys, &dummy); @@ -123,9 +166,8 @@ child = UPA_RANGE_CHILD(&ur[i]); if (UPA_RANGE_CS(&ur[i]) == cs && phys >= child && phys - child < UPA_RANGE_SIZE(&ur[i])) { - cn_phys = phys; - cn_bushandle = sparc64_fake_bustag(bs, - UPA_RANGE_PHYS(&ur[i]) + phys, &cn_bustag); + se_cnhandle = sparc64_fake_bustag(bs, + UPA_RANGE_PHYS(&ur[i]) + phys, &se_cntag); error = 0; break; } @@ -138,20 +180,23 @@ { phandle_t parent; phandle_t node; + phandle_t root; char name[8]; + int channel; int disabled; int flags; - int unit; disabled = 0; cn->cn_pri = CN_DEAD; - if ((node = OF_peer(0)) <= 0 || - (node = OF_traverse(node, se_cnfind)) <= 0) + if ((root = OF_peer(0)) == -1 || + OF_traverse(root, &node, se_cnfind) == -1) return; - for (unit = 0; unit < SE_UNITS; unit++) { - if (resource_int_value("se", unit, "disabled", &disabled) != 0) + for (channel = 0; channel < SE_CHANNELS; channel++) { + if (resource_int_value("se", channel, "disabled", + &disabled) != 0) { disabled = 0; - if (resource_int_value("se", unit, "flags", &flags) == 0) { + } + if (resource_int_value("se", channel, "flags", &flags) == 0) { if (!disabled && SE_CONSOLE(flags)) goto map; } @@ -166,31 +211,110 @@ return; if (se_cnmap(node, parent) != 0) return; -#if 0 - cn->cn_dev = makedev(CDEV_MAJOR, unit); + se_cnchan = (channel == 0 ? SE_CHA : SE_CHB); + + cn->cn_dev = makedev(CDEV_MAJOR, channel); cn->cn_pri = SE_FORCECONSOLE(flags) || boothowto & RB_SERIAL ? CN_REMOTE : CN_NORMAL; -#endif } static void se_cninit(struct consdev *cn) { + u_char ccr0; + + /* + * Power down the chip for initialization. + */ + SE_CNWRITE_1(SE_CCR0, 0x0); + + /* + * Now program the chip for polled asynchronous serial io. + */ + SE_CNWRITE_1(SE_CCR0, CCR0_MCE | CCR0_SM_ASYNC); + SE_CNWRITE_1(SE_CMDR, CMDR_RRES | CMDR_XRES); + SE_CNWRITE_1(SE_CCR1, CCR1_ODS | CCR1_BCR | CCR1_CM_7); + SE_CNWRITE_1(SE_BGR, SE_DIV(48, 2)); + SE_CNWRITE_1(SE_CCR2, CCR2_TOE | CCR2_SSEL | CCR2_BDF); + SE_CNWRITE_1(SE_CCR3, 0x0); + SE_CNWRITE_1(SE_CCR4, CCR4_EBRG | CCR4_MCK4); + SE_CNWRITE_1(SE_MODE, MODE_FCTS | MODE_RAC | MODE_RTS); + SE_CNWRITE_1(SE_DAFO, DAFO_CHL_8); + SE_CNWRITE_1(SE_RFC, RFC_DPS | RFC_RFTH_32); + SE_CNWRITE_1(SE_IPC, IPC_VIS); + + /* + * Now power up the chip again. + */ + ccr0 = SE_CNREAD_1(SE_CCR0); + ccr0 |= CCR0_PU; + SE_CNWRITE_1(SE_CCR0, ccr0); + + SE_CNWRITE_1(SE_CMDR, CMDR_RRES | CMDR_XRES); } static int se_cngetc(dev_t dev) { - return (0); + u_char c; + + while ((SE_CNREAD_1(SE_STAR) & (STAR_CEC | STAR_RFNE)) != STAR_RFNE) + ; + SE_CNWRITE_1(SE_CMDR, CMDR_RFRD); + while ((SE_CNREAD_1(SE_ISR0) & ISR0_TCD) == 0) + ; + c = SE_CNREAD_1(SE_RFIFO); + SE_CNWRITE_1(SE_CMDR, CMDR_RMC); + return (c); } static int se_cncheckc(dev_t dev) { - return (0); + u_char c; + + if ((SE_CNREAD_1(SE_STAR) & STAR_RFNE) != 0) { + while ((SE_CNREAD_1(SE_STAR) & STAR_CEC) != 0) + ; + SE_CNWRITE_1(SE_CMDR, CMDR_RFRD); + while ((SE_CNREAD_1(SE_ISR0) & ISR0_TCD) == 0) + ; + c = SE_CNREAD_1(SE_RFIFO); + SE_CNWRITE_1(SE_CMDR, CMDR_RMC); + return (c); + } + return (-1); } static void se_cnputc(dev_t dev, int c) { + + while ((SE_CNREAD_1(SE_STAR) & (STAR_CTS | STAR_CEC | STAR_XFW)) != + (STAR_CTS | STAR_XFW)) + ; + SE_CNWRITE_1(SE_XFIFO, c); + SE_CNWRITE_1(SE_CMDR, CMDR_XF); +} + +static void +se_cnregdump(void) +{ + + CTR1(KTR_SE, "se_cnprobe: mode=%#x", SE_CNREAD_1(SE_MODE)); + CTR1(KTR_SE, "se_cnprobe: timr=%#x", SE_CNREAD_1(SE_TIMR)); + CTR1(KTR_SE, "se_cnprobe: xon=%#x", SE_CNREAD_1(SE_XON)); + CTR1(KTR_SE, "se_cnprobe: xoff=%#x", SE_CNREAD_1(SE_XOFF)); + CTR1(KTR_SE, "se_cnprobe: tcr=%#x", SE_CNREAD_1(SE_TCR)); + CTR1(KTR_SE, "se_cnprobe: dafo=%#x", SE_CNREAD_1(SE_DAFO)); + CTR1(KTR_SE, "se_cnprobe: rfc=%#x", SE_CNREAD_1(SE_RFC)); + CTR1(KTR_SE, "se_cnprobe: ccr0=%#x", SE_CNREAD_1(SE_CCR0)); + CTR1(KTR_SE, "se_cnprobe: ccr1=%#x", SE_CNREAD_1(SE_CCR1)); + CTR1(KTR_SE, "se_cnprobe: ccr2=%#x", SE_CNREAD_1(SE_CCR2)); + CTR1(KTR_SE, "se_cnprobe: ccr3=%#x", SE_CNREAD_1(SE_CCR3)); + CTR1(KTR_SE, "se_cnprobe: vstr=%#x", SE_CNREAD_1(SE_VSTR)); + CTR1(KTR_SE, "se_cnprobe: ipc=%#x", SE_CNREAD_1(SE_IPC)); + CTR1(KTR_SE, "se_cnprobe: ccr4=%#x", SE_CNREAD_1(SE_CCR4)); } + +#endif ==== //depot/projects/sparc64/sys/dev/se/sereg.h#4 (text+ko) ==== @@ -29,6 +29,8 @@ #ifndef _DEV_SE_SEREG_H_ #define _DEV_SE_SEREG_H_ +#define SE_DIV(n, m) (((m) << 6) | ((n) - 1)) + #define SE_CHA 0x0 /* channel a offset */ #define SE_CHB 0x40 /* channel b offset */ @@ -36,83 +38,86 @@ #define SE_XFIFO 0x0 /* transmit fifo */ #define SE_STAR 0x20 /* status register */ -#define STAR_WFA 0x1 /* wait for acknowledgement */ #define STAR_CTS 0x2 /* clear to send state */ #define STAR_CEC 0x4 /* command executing */ -#define STAR_RLI 0x8 /* receive line inactive */ -#define STAR_RRNR 0x10 /* receive receiver not ready */ -#define STAR_XRNR 0x20 /* transmit receiver not ready */ +#define STAR_TEC 0x8 /* tic executing */ +#define STAR_FCS 0x10 /* flow control status */ +#define STAR_RFNE 0x20 /* receive fifo not empty */ #define STAR_XFW 0x40 /* transmit fifo write enable */ #define STAR_XDOV 0x80 /* transmit data overflow */ #define SE_CMDR 0x20 /* command register */ #define CMDR_XRES 0x1 /* transmitter reset */ -#define CMDR_XME 0x2 /* transmit message end */ -#define CMDR_XIF 0x4 /* transmit i-frame */ -#define CMDR_XTF 0x8 /* transmit transparent frame */ +#define CMDR_XF 0x8 /* transmit frame */ #define CMDR_STI 0x10 /* start timer */ -#define CMDR_XREP 0x20 /* transmission repeat */ -#define CMDR_RHR 0x40 /* reset hdlc receiver */ +#define CMDR_RFRD 0x20 /* receive fifo read enable */ +#define CMDR_RRES 0x40 /* reveiver reset */ #define CMDR_RMC 0x80 /* receive message complete */ -#define SE_RSTA 0x21 /* receive status */ -#define RSTA_LA 0x1 /* low byte address compare */ -#define RSTA_CR 0x2 /* command/response */ -#define RSTA_HA0 0x4 /* high byte address compare 0 */ -#define RSTA_HA1 0x8 /* high byte address compare 1 */ -#define RSTA_RAB 0x10 /* receive message aborted */ -#define RSTA_CRC 0x20 /* crc compare/check */ -#define RSTA_RDO 0x40 /* receive data overflow */ -#define RSTA_VFR 0x80 /* valid frame */ - -#define SE_PRE 0x21 /* preamble register */ - #define SE_MODE 0x22 /* mode register */ #define MODE_TLP 0x1 /* test loop */ #define MODE_TRS 0x2 /* timer resolution */ #define MODE_RTS 0x4 /* request to send */ #define MODE_RAC 0x8 /* receiver active */ -#define MODE_TMD 0x10 /* timer mode */ -#define MODE_ADM 0x20 /* address mode */ -#define MODE_MDS0 0x40 /* mode select 0 */ -#define MODE_MDS1 0x80 /* mode select 1 */ +#define MODE_FLON 0x10 /* flow control on */ +#define MODE_FCTS 0x20 /* flow control using cts */ +#define MODE_FRTS 0x40 /* flow control using rts */ #define SE_TIMR 0x23 /* timer register */ -#define SE_XAD1 0x24 /* transmit address 1 */ -#define SE_XAD2 0x25 /* transmit address 2 */ -#define SE_RAH1 0x26 /* receive address high 1 */ -#define SE_RAH2 0x27 /* receive address high 2 */ -#define SE_RAL1 0x28 /* receive address low 1 */ -#define SE_RHCR 0x29 /* receive hdlc control */ -#define SE_RAL2 0x29 /* receive address low 2 */ +#define SE_XON 0x24 /* xon character */ +#define SE_XOFF 0x25 /* xoff character */ +#define SE_TCR 0x26 /* transmit character register */ + +#define SE_DAFO 0x27 /* data format */ +#define DAFO_CHL 0x2 /* character length */ +#define DAFO_CHL_8 0x0 /* 8 bits */ +#define DAFO_CHL_7 0x1 /* 7 bits */ +#define DAFO_CHL_6 0x2 /* 6 bits */ +#define DAFO_CHL_5 0x3 /* 5 bits */ +#define DAFO_PARE 0x4 /* parity enable */ +#define DAFO_PAR 0x18 /* parity format */ +#define DAFO_STOP 0x20 /* stop bit */ +#define DAFO_XBRK 0x40 /* transmit break */ + +#define SE_RFC 0x28 /* rfifo control register */ +#define RFC_TCDE 0x1 /* termination character detection enable */ +#define RFC_RFTH 0xc /* rfifo threshold level */ +#define RFC_RFTH_2 0x0 /* 2 bytes */ +#define RFC_RFTH_4 0x4 /* 4 bytes */ +#define RFC_RFTH_16 0x8 /* 16 bytes */ +#define RFC_RFTH_32 0xc /* 32 bytes */ +#define RFC_RFDF 0x10 /* rfifo data format */ +#define RFC_DXS 0x20 /* disable storage of xon/xoff characters */ +#define RFC_DPS 0x40 /* disable parity storage */ + #define SE_RBCL 0x2a /* receive byte count low */ #define SE_XBCL 0x2a /* transmit byte count low */ #define SE_RBCH 0x2b /* receive byte count high */ #define SE_XBCH 0x2b /* transmit byte count high */ #define SE_CCR0 0x2c /* channel configuration register 0 */ -#define CCR0_SM0 0x1 /* serial mode 0 */ -#define CCR0_SM1 0x2 /* serial mode 1 */ -#define CCR0_SC0 0x4 /* serial configuration 0 */ -#define CCR0_SC1 0x8 /* serial configuration 1 */ -#define CCR0_SC2 0x10 /* serial configuration 2 */ -#define CCR0_UNUSED0 0x20 /* unused */ -#define CCR0_MSE 0x40 /* master clock enable */ +#define CCR0_SM 0x3 /* serial mode */ +#define CCR0_SM_HDLC 0x0 /* hdlc/sdlc mode */ +#define CCR0_SM_SDLC 0x1 /* sdlc loop mode */ +#define CCR0_SM_BISYNC 0x2 /* bisync mode */ +#define CCR0_SM_ASYNC 0x3 /* async mode */ +#define CCR0_SC 0x1c /* serial configuration */ +#define CCR0_SC_NRZ 0x0 /* nrz data encoding */ +#define CCR0_SC_NRZI 0x2 /* nrzi data encoding */ +#define CCR0_SC_FM0 0x4 /* fm0 data encoding */ +#define CCR0_SC_FM1 0x5 /* fm1 data encoding */ +#define CCR0_SC_MCHSTR 0x6 /* manchester data encoding */ +#define CCR0_MCE 0x40 /* master clock enable */ #define CCR0_PU 0x80 /* power up */ #define SE_CCR1 0x2d /* channel configuration register 1 */ -#define CCR1_CM0 0x1 /* clock mode 0 */ -#define CCR1_CM1 0x2 /* clock mode 1 */ -#define CCR1_CM2 0x4 /* clock mode 2 */ -#define CCR1_ITF 0x8 /* interframe time fill */ +#define CCR1_CM 0x7 /* clock mode */ +#define CCR1_CM_7 0x7 /* clock mode 7 */ +#define CCR1_BCR 0x8 /* bit clock rate */ #define CCR1_ODS 0x10 /* output driver select */ -#define CCR1_GLP 0x20 /* go on loop */ -#define CCR1_GALP 0x40 /* go active on loop */ -#define CCR1_SFLG 0x80 /* enable shared flags */ #define SE_CCR2 0x2e /* channel configuration register 2 */ #define CCR2_DIV 0x1 /* data inversion */ -#define CCR2_C32 0x2 /* enable crc32 */ #define CCR2_RWX 0x4 /* read/write exchange */ #define CCR2_TOE 0x8 /* txclk ouput enable */ #define CCR2_SSEL 0x10 /* clock source select */ @@ -126,13 +131,6 @@ #define SE_CCR3 0x2f /* channel configuration register 3 */ #define CCR3_PSD 0x1 /* dpll phase shift disable */ -#define CCR3_XCRC 0x2 /* transmit crc on/off */ -#define CCR3_RCRC 0x4 /* receive crc on/off */ -#define CCR3_CRL 0x8 /* crc reset level */ -#define CCR3_RADD 0x10 /* receive address pushed to rfifo */ -#define CCR3_EPT 0x20 /* enable preamble transmission */ -#define CCR3_PRE0 0x40 /* number of preamble repetition 0 */ -#define CCR3_PRE1 0x80 /* number of preamble repetition 1 */ #define SE_TSAX 0x30 /* transmit timeslot assignment register */ #define SE_TSAR 0x31 /* receive timeslot assignment register */ @@ -140,28 +138,20 @@ #define SE_RCCR 0x33 /* receive channel capacity register */ #define SE_VSTR 0x34 /* version status register */ -#define VSTR_VN0 0x1 /* version number 0 */ -#define VSTR_VN1 0x2 /* version number 1 */ -#define VSTR_VN2 0x4 /* version number 2 */ -#define VSTR_VN3 0x8 /* version number 3 */ -#define VSTR_UNUSED0 0x10 /* unused */ -#define VSTR_UNUSED1 0x20 /* unused */ +#define VSTR_VN 0xf /* version number 0 */ #define VSTR_DPLA 0x40 /* dpll asynchronous */ #define VSTR_CD 0x80 /* carrier detect */ #define SE_BGR 0x34 /* baud rate generator register */ -#define SE_RLCR 0x35 /* receive frame length check */ -#define SE_AML 0x36 /* address mask low */ -#define SE_AMH 0x37 /* address mask high */ +#define SE_TIC 0x35 /* trasmit immediate character */ +#define SE_MXN 0x36 /* mask xon character */ +#define SE_MXF 0x37 /* mask xoff character */ #define SE_GIS 0x38 /* global interrupt status */ #define GIS_ISB0 0x1 /* interrupt status channel B 0 */ #define GIS_ISB1 0x2 /* interrupt status channel B 1 */ #define GIS_ISA0 0x4 /* interrupt status channel A 0 */ #define GIS_ISA1 0x8 /* interrupt status channel A 1 */ -#define GIS_UNUSED0 0x10 /* unused */ -#define GIS_UNUSED1 0x20 /* unused */ -#define GIS_UNUSED2 0x40 /* unused */ #define GIS_PI 0x80 /* univerisal port interrupt */ #define SE_IVA 0x38 /* interrupt vector address */ @@ -172,8 +162,6 @@ #define IPC_CASM 0x4 /* cascading mode */ #define IPC_SLA0 0x8 /* slave address 0 */ #define IPC_SLA1 0x10 /* slave address 1 */ -#define IPC_UNUSED0 0x20 /* unused */ -#define IPC_UNUSED1 0x40 /* unused */ #define IPC_VIS 0x80 /* masked interrupts visible */ #define SE_ISR0 0x3a /* interrupt status 0 */ @@ -181,22 +169,22 @@ #define ISR0_RFO 0x2 /* receive frame overflow */ #define ISR0_CDSC 0x4 /* carrier detect status change */ #define ISR0_PLLA 0x8 /* dpll asynchronous */ -#define ISR0_PCE 0x10 /* protocol error */ -#define ISR0_RSC 0x20 /* receive status change */ -#define ISR0_RFS 0x40 /* receive frame start */ -#define ISR0_RME 0x80 /* receive frame end */ +#define ISR0_FERR 0x10 /* framing error */ +#define ISR0_PERR 0x20 /* parity error */ +#define ISR0_TIME 0x40 /* time out */ +#define ISR0_TCD 0x80 /* termination character detected */ #define SE_IMR0 0x3a /* interrupt mask 0 */ #define SE_ISR1 0x3b /* interrupt status 1 */ #define ISR1_XPR 0x1 /* transmit pool ready */ -#define ISR1_XMR 0x2 /* transmit message repeat */ +#define ISR1_XON 0x2 /* transmit message repeat */ #define ISR1_CSC 0x4 /* clear to send status change */ #define ISR1_TIN 0x8 /* timer interrupt */ -#define ISR1_XDU 0x10 /* transmit data underrun */ -#define ISR1_AOLP 0x20 /* active on loop */ -#define ISR1_OLP 0x40 /* on loop */ -#define ISR1_EOP 0x80 /* end of poll sequence detected */ +#define ISR1_XOFF 0x10 /* xoff character detected */ +#define ISR1_ALLS 0x20 /* all sent */ +#define ISR1_BRKT 0x40 /* break terminated */ +#define ISR1_BRK 0x80 /* break */ #define SE_IMR1 0x3b /* interrupt mask 1 */ #define SE_PVR 0x3c /* port value register */ @@ -205,10 +193,6 @@ #define SE_PCR 0x3e /* port configuration register */ #define SE_CCR4 0x3f /* channel configuration register 4 */ -#define CCR4_RFT0 0x1 /* rfifo threshold level 0 */ -#define CCR4_RFT1 0x2 /* rfifo threshold level 1 */ -#define CCR4_UNUSED0 0x4 /* unused */ -#define CCR4_UNUSED1 0x8 /* unused */ #define CCR4_ICD 0x10 /* invert polarity of carrier detect signal */ #define CCR4_TST1 0x20 /* test pin */ #define CCR4_EBRG 0x40 /* enhanced baud rate generator mode */ To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe p4-projects" in the body of the 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