From owner-svn-src-head@FreeBSD.ORG Wed Oct 9 00:27:12 2013 Return-Path: Delivered-To: svn-src-head@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTP id EB132758; Wed, 9 Oct 2013 00:27:12 +0000 (UTC) (envelope-from adrian@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.freebsd.org (Postfix) with ESMTPS id BE72C2D22; Wed, 9 Oct 2013 00:27:12 +0000 (UTC) Received: from svn.freebsd.org ([127.0.1.70]) by svn.freebsd.org (8.14.7/8.14.7) with ESMTP id r990RCEo071553; Wed, 9 Oct 2013 00:27:12 GMT (envelope-from adrian@svn.freebsd.org) Received: (from adrian@localhost) by svn.freebsd.org (8.14.7/8.14.5/Submit) id r990RCsv071545; Wed, 9 Oct 2013 00:27:12 GMT (envelope-from adrian@svn.freebsd.org) Message-Id: <201310090027.r990RCsv071545@svn.freebsd.org> From: Adrian Chadd Date: Wed, 9 Oct 2013 00:27:12 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r256172 - head/sys/mips/include X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 09 Oct 2013 00:27:13 -0000 Author: adrian Date: Wed Oct 9 00:27:12 2013 New Revision: 256172 URL: http://svnweb.freebsd.org/changeset/base/256172 Log: Add "better" MIPS24k and MIPS74k barriers. * the mips74k cores only need EHB (which is 'sll $0, $0, 3') here; NOPs don't actually work. * add EHB as the last NOP for the default barriers/hazards; that is "better" behaviour and should work on a wider variety of processors. This allows the existing (icky) TLB code to work, allowing the AR9344 SoC (mips74k) to actually get through kernel startup. Tested: * AR9344 SoC - (mips74k) * AR9331 SoC - (mips24k) TODO: * test on mips4k CPUs, just to be sure. * document that sll $0, $0, 3 is actually "EHB" and that it falls back to being a NOP for pre-mips32r1. * mips24k has an errata that we currently don't correctly explicitly state - ie, that after DERET/ERET, the only valid instruction is a NOP. Reviewed by: imp@ Approved by: re@ (gjb) Modified: head/sys/mips/include/asm.h head/sys/mips/include/cpuregs.h Modified: head/sys/mips/include/asm.h ============================================================================== --- head/sys/mips/include/asm.h Wed Oct 9 00:22:21 2013 (r256171) +++ head/sys/mips/include/asm.h Wed Oct 9 00:27:12 2013 (r256172) @@ -725,9 +725,12 @@ _C_LABEL(x): #elif defined(CPU_RMI) #define HAZARD_DELAY #define ITLBNOPFIX +#elif defined(CPU_MIPS74KC) +#define HAZARD_DELAY sll $0,$0,3 +#define ITLBNOPFIX sll $0,$0,3 #else -#define ITLBNOPFIX nop;nop;nop;nop;nop;nop;nop;nop;nop;nop; -#define HAZARD_DELAY nop;nop;nop;nop;nop; +#define ITLBNOPFIX nop;nop;nop;nop;nop;nop;nop;nop;nop;sll $0,$0,3; +#define HAZARD_DELAY nop;nop;nop;nop;sll $0,$0,3; #endif #endif /* !_MACHINE_ASM_H_ */ Modified: head/sys/mips/include/cpuregs.h ============================================================================== --- head/sys/mips/include/cpuregs.h Wed Oct 9 00:22:21 2013 (r256171) +++ head/sys/mips/include/cpuregs.h Wed Oct 9 00:27:12 2013 (r256172) @@ -149,6 +149,11 @@ #define MIPS_CCA_CC 0x05 /* Cacheable Coherent. */ #endif +#if defined(CPU_MIPS74KC) +#define MIPS_CCA_UNCACHED 0x02 +#define MIPS_CCA_CACHED 0x00 +#endif + #ifndef MIPS_CCA_UNCACHED #define MIPS_CCA_UNCACHED MIPS_CCA_UC #endif @@ -204,12 +209,14 @@ #define COP0_SYNC .word 0xc0 /* ehb */ #elif defined(CPU_SB1) #define COP0_SYNC ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop +#elif defined(CPU_MIPS74KC) +#define COP0_SYNC .word 0xc0 /* ehb */ #else /* * Pick a reasonable default based on the "typical" spacing described in the * "CP0 Hazards" chapter of MIPS Architecture Book Vol III. */ -#define COP0_SYNC ssnop; ssnop; ssnop; ssnop; ssnop +#define COP0_SYNC ssnop; ssnop; ssnop; ssnop; .word 0xc0; #endif #define COP0_HAZARD_FPUENABLE nop; nop; nop; nop;