Date: Fri, 13 Oct 2023 23:14:24 GMT From: Ed Maste <emaste@FreeBSD.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-branches@FreeBSD.org Subject: git: e8d85401cd8d - releng/14.0 - x86: Add defines for workaround bits in AMD's MSR "Decode Configuration" Message-ID: <202310132314.39DNEOp4064763@gitrepo.freebsd.org>
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The branch releng/14.0 has been updated by emaste: URL: https://cgit.FreeBSD.org/src/commit/?id=e8d85401cd8dbc88a822d9c54086c7526fb620f7 commit e8d85401cd8dbc88a822d9c54086c7526fb620f7 Author: Olivier Certner <olce.freebsd@certner.fr> AuthorDate: 2023-09-11 13:10:35 +0000 Commit: Ed Maste <emaste@FreeBSD.org> CommitDate: 2023-10-13 23:14:00 +0000 x86: Add defines for workaround bits in AMD's MSR "Decode Configuration" They are a bit more informative than raw hexadecimal values. While here, sort existing defines of bits for AMD MSRs to match the address order. Reviewed by: kib, emaste Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D41816 (cherry picked from commit 125bbadf6084ac341673c9eb1979a740d3d5899a) (cherry picked from commit d0c0dcf9db7e558a58fbec2d49c293d118ea6979) Approved by: re (gjb) --- sys/amd64/amd64/initcpu.c | 5 +++-- sys/x86/include/specialreg.h | 9 +++++++-- 2 files changed, 10 insertions(+), 4 deletions(-) diff --git a/sys/amd64/amd64/initcpu.c b/sys/amd64/amd64/initcpu.c index 4debe89426df..a048c08fc9ae 100644 --- a/sys/amd64/amd64/initcpu.c +++ b/sys/amd64/amd64/initcpu.c @@ -101,7 +101,8 @@ init_amd(void) case 0x10: case 0x12: if ((cpu_feature2 & CPUID2_HV) == 0) - wrmsr(MSR_DE_CFG, rdmsr(MSR_DE_CFG) | 1); + wrmsr(MSR_DE_CFG, rdmsr(MSR_DE_CFG) | + DE_CFG_10H_12H_STACK_POINTER_JUMP_FIX_BIT); break; } @@ -151,7 +152,7 @@ init_amd(void) (cpu_feature2 & CPUID2_HV) == 0) { /* 1021 */ msr = rdmsr(MSR_DE_CFG); - msr |= 0x2000; + msr |= DE_CFG_ZEN_LOAD_STALE_DATA_FIX_BIT; wrmsr(MSR_DE_CFG, msr); /* 1033 */ diff --git a/sys/x86/include/specialreg.h b/sys/x86/include/specialreg.h index 548d6010e7b8..f45990a056c8 100644 --- a/sys/x86/include/specialreg.h +++ b/sys/x86/include/specialreg.h @@ -1162,11 +1162,16 @@ #define MSR_IC_CFG 0xc0011021 /* Instruction Cache Configuration */ #define MSR_DE_CFG 0xc0011029 /* Decode Configuration */ +/* MSR_AMDK8_IPM */ +#define AMDK8_SMIONCMPHALT (1ULL << 27) +#define AMDK8_C1EONCMPHALT (1ULL << 28) + /* MSR_VM_CR related */ #define VM_CR_SVMDIS 0x10 /* SVM: disabled by BIOS */ -#define AMDK8_SMIONCMPHALT (1ULL << 27) -#define AMDK8_C1EONCMPHALT (1ULL << 28) +/* MSR_DE_CFG */ +#define DE_CFG_10H_12H_STACK_POINTER_JUMP_FIX_BIT 0x1 +#define DE_CFG_ZEN_LOAD_STALE_DATA_FIX_BIT 0x2000 /* VIA ACE crypto featureset: for via_feature_rng */ #define VIA_HAS_RNG 1 /* cpu has RNG */
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