Date: Sun, 13 Oct 2002 12:00:35 -0700 (PDT) From: Matthew Dillon <dillon@apollo.backplane.com> To: "M. Warner Losh" <imp@bsdimp.com> Cc: tlambert2@mindspring.com, ticso@cicely.de, hch@infradead.org, wes@softweyr.com, vova@sw.ru, nate@root.org, arch@FreeBSD.org Subject: Re: Database indexes and ram Message-ID: <200210131900.g9DJ0ZAM054777@apollo.backplane.com> References: <3DA954CF.98B0891A@mindspring.com> <20021013.060851.113437955.imp@bsdimp.com> <3DA9B4A8.194A02FC@mindspring.com> <20021013.120847.31902907.imp@bsdimp.com>
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Google is your friend. I found a quick reference on the PCI bus.
A 32 bit PCI bus can support 64 bit addresses through the use of
two address cycles prefacing the data transfer.
That said, we all know how shoddy a large chunk of the PCI market is
(well, really the *entire* PC market, not just PCI). Just because the
spec allows it doesn't mean the chipset/motherboards support it or,
more importantly, support it reliably. Remember all the cache/MMU bugs
that showed up in the 486 series when people started actually using the
MMU?
IMHO as much as I like the coolness of throwing more then 4G into a PC
not really designed to take more then 4G, I personally believe that
it is wiser to distribute processing at that point rather then spend
money on more specialized (and finicky) configurations. You will see
me throw more then 4G into a box when the next generation capable of
dealing with more then 4G becomes commoditized.
-Matt
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