Date: Thu, 18 Jul 2013 07:06:43 +0900 From: =?UTF-8?Q?Iori=E3=80=80YONEJI?= <fivo.11235813@gmail.com> To: soc-status@freebsd.org Subject: GSoC status Week 4 Message-ID: <CAJ-Y7VddBj5Jn8FvG_r-WXUV7foc=DZ59QAYcW6E8FiJ9Khe=Q@mail.gmail.com>
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Hi, sorry for absence of contact on soc-status list. I had term-exam at first week, so progress is not so fast but mostly as fast as I thought at first. I have contacted with Neel, but I realized that I must post on soc-status, so I show you my progress I sent to Neel before, and I discuss more detail about that below. == Quote == I'm facing two task in this project. 1. to make a call chain to issue suspend command from userland to kernel 2. to rewrite abstract registers definition that I wrote before First, about 1, I made userland simple command to issue new ioctl()*A call through new vmmapi function, *B but this ioctl() handler produce general protection failure every time. This is because a struct of registers to be saved transmission goes something mistaken, but I'm not sure how to fix it now. So I'm reading other codes transfer a struct to userland and looking for documents. Secondly, about 2, I have made a virtual machine's savable registers definition, and I'm using this in task 1 above,but it was imperfect, so I rewrote this and mostly done. *A ioctl(ctx->fd, VM_GET_VCPUSTATE, vmstate); *B vm_get_allvstate(struct vmctx *ctx, struct vmstate *vmstate) And I have these code in local repository, but I don't know how frequently I should commit to the freebsd repository, anyways, I will commit them if 1's transmission goes well. == Quote end == About problem 1, I knew that General Protection Fault is caused at copyout() function, but it seems a little hard to find good books that show what's exactly going on with copyout() and copyin(). Do you know some documents about them? Second, problem 2 is done, referring to Intel SDM Vol1. Chapter 3 and Vol3. Chapter 24. This registers definition is containing some 'hidden' fields of special registers(like GDTR), so it is a little bit depending on Intel's implementation. In the future work with AMD's CPU, this struct might be changed. Thanks, Iori.
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