From owner-freebsd-hackers@FreeBSD.ORG Wed Apr 20 20:39:39 2005 Return-Path: Delivered-To: freebsd-hackers@freebsd.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id 2C68E16A4CE for ; Wed, 20 Apr 2005 20:39:39 +0000 (GMT) Received: from serl.cs.colorado.edu (serl.cs.colorado.edu [128.138.207.163]) by mx1.FreeBSD.org (Postfix) with ESMTP id DB47C43D48 for ; Wed, 20 Apr 2005 20:39:38 +0000 (GMT) (envelope-from John.Giacomoni@colorado.edu) Received: from [IPv6???1] (localhost [127.0.0.1]) by serl.cs.colorado.edu (Postfix) with ESMTP id BD98F590CC for ; Wed, 20 Apr 2005 14:39:39 -0600 (MDT) Mime-Version: 1.0 (Apple Message framework v622) Content-Transfer-Encoding: 7bit Message-Id: Content-Type: text/plain; charset=US-ASCII; format=flowed To: freebsd-hackers@freebsd.org From: John Giacomoni Date: Wed, 20 Apr 2005 14:39:35 -0600 X-Mailer: Apple Mail (2.622) Subject: what goes wrong with barrier free atomic_load/store? X-BeenThere: freebsd-hackers@freebsd.org X-Mailman-Version: 2.1.1 Precedence: list List-Id: Technical Discussions relating to FreeBSD List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 20 Apr 2005 20:39:39 -0000 in reading /src/sys/i386/include/atomic.h I found this comment and I'm having trouble understanding what the problem being referred to below is. /* * We assume that a = b will do atomic loads and stores. However, on a * PentiumPro or higher, reads may pass writes, so for that case we have * to use a serializing instruction (i.e. with LOCK) to do the load in * SMP kernels. For UP kernels, however, the cache of the single processor * is always consistent, so we don't need any memory barriers. */ can someone give me an example of a situation where one needs to use memory barriers to ensure "correctness" when doing writes as above? the examples I can come up with seem to boil down to requiring locks or accepting stale values, given that without a synchronization mechanism one shouldn't expect two processes to act in any specific order. In my case I can accept reading a stale value so I'm not understanding the purpose of only having atomic_load/atomic_store wrappers with memory barriers. I saw a brief discussion where someone proposed barrier free load/store but don't think I saw any resolution. thanks, John G -- John.Giacomoni@colorado.edu University of Colorado at Boulder Department of Computer Science Engineering Center, ECCS 121 430 UCB Boulder, CO 80303-0430 USA