Date: Tue, 5 Aug 1997 09:15:54 -0700 (MST) From: Terry Lambert <terry@lambert.org> To: tony@dell.com (Tony Overfield) Cc: terry@lambert.org, hackers@FreeBSD.ORG Subject: Re: Pentium II? Message-ID: <199708051615.JAA06274@phaeton.artisoft.com> In-Reply-To: <3.0.2.32.19970804125532.0070d730@bugs.us.dell.com> from "Tony Overfield" at Aug 4, 97 12:55:32 pm
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> >Yes, I can. Search for "PCI" instead of "Dell"; this was a property > >of the Saturn I, Neptune I, and Mecury I chipsets, not a property > >of only Dell computers -- any computer using those chips blew the > >cache line invalidation following a DMA from a PCI controller to > >main memory. > > Except that there were work-arounds for the problems which we > implemented. It's simply not true that all of those systems > had those problems. Ugh. The workarounds were unaceptable. If I used PCI bus mastering, my normal performance was reduced by an IMO significant amount. > >> Don't forget than Pentium memory is 64 bits wide and 486/50 memory > >> is 32 bits wide. Thus, your fancy 486/50 memory bus cannot help to > >> explain your faster I/O claims, so maybe you've got a "magic I/O bus." > > > >Actually, PCI busses are only 32 bits wide, so the 64 bit processor > >memory path is totally irrelevent for bus master DMA speed. The > >width limitation is at the bus-to-memory interface, not at the > >processor. > > No. PCI memory writes are often posted, combined and written into > DRAM 64 bits at a time. I could see where this might have an effect... IFF there were wait states on writing memory from PCI that the posting worked around. However, I would expect it to have less than 25% of the impact that an actual 64 bit data path had, were that the case. Regards, Terry Lambert terry@lambert.org --- Any opinions in this posting are my own and not those of my present or previous employers.
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