From owner-svn-src-all@FreeBSD.ORG Sat Mar 21 06:00:47 2015 Return-Path: Delivered-To: svn-src-all@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id 6785C1B6; Sat, 21 Mar 2015 06:00:47 +0000 (UTC) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 5328E9D5; Sat, 21 Mar 2015 06:00:47 +0000 (UTC) Received: from svn.freebsd.org ([127.0.1.70]) by svn.freebsd.org (8.14.9/8.14.9) with ESMTP id t2L60lNQ008046; Sat, 21 Mar 2015 06:00:47 GMT (envelope-from adrian@FreeBSD.org) Received: (from adrian@localhost) by svn.freebsd.org (8.14.9/8.14.9/Submit) id t2L60lsI008045; Sat, 21 Mar 2015 06:00:47 GMT (envelope-from adrian@FreeBSD.org) Message-Id: <201503210600.t2L60lsI008045@svn.freebsd.org> X-Authentication-Warning: svn.freebsd.org: adrian set sender to adrian@FreeBSD.org using -f From: Adrian Chadd Date: Sat, 21 Mar 2015 06:00:47 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r280314 - head/sys/mips/atheros X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 21 Mar 2015 06:00:47 -0000 Author: adrian Date: Sat Mar 21 06:00:46 2015 New Revision: 280314 URL: https://svnweb.freebsd.org/changeset/base/280314 Log: add QCA955x PCIe configuration registers. These are /not/ absolute addresses, as the QCA955x SoC has 2 PCIe RC's (and 1 PCIe EP.) Modified: head/sys/mips/atheros/qca955xreg.h Modified: head/sys/mips/atheros/qca955xreg.h ============================================================================== --- head/sys/mips/atheros/qca955xreg.h Sat Mar 21 05:59:45 2015 (r280313) +++ head/sys/mips/atheros/qca955xreg.h Sat Mar 21 06:00:46 2015 (r280314) @@ -205,4 +205,14 @@ #define QCA955X_DDR_REG_FLUSH_PCIE (AR71XX_APB_BASE + 0xa8) #define QCA955X_DDR_REG_FLUSH_WMAC (AR71XX_APB_BASE + 0xac) +/* PCIe control block - relative to PCI_CTRL_BASE0/PCI_CTRL_BASE1 */ + +#define QCA955X_PCI_APP 0x0 +#define QCA955X_PCI_APP_LTSSM_ENABLE (1 << 0) +#define QCA955X_PCI_RESET 0x18 +#define QCA955X_PCI_RESET_LINK_UP (1 << 0) +#define QCA955X_PCI_INTR_STATUS 0x4c +#define QCA955X_PCI_INTR_MASK 0x50 +#define QCA955X_PCI_INTR_DEV0 (1 << 14) + #endif /* __QCA955XREG_H__ */