From nobody Mon Oct 27 12:02:27 2025 X-Original-To: dev-commits-src-all@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4cwBvl4QGmz6DS2w; Mon, 27 Oct 2025 12:02:27 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "R12" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4cwBvl2RCjz3CMp; Mon, 27 Oct 2025 12:02:27 +0000 (UTC) (envelope-from git@FreeBSD.org) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1761566547; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=PTSmBUT+NSU0Pf3UvTw6VzFlnJ/x+0CdayRPcxXKwSA=; b=ZFMGwZG77KGZTKcCWU5BdW9fCre3SV4CmUNbgsYOCXYBi9pAnBJUsehnC//WZvAGu34PeP COxzS2n4NJVdaQwrxRRxc+Q7urdAEe2OvSX3a3sfgBZh+CSGB6iWcrNhZeKBj2DaLDq4Vm 0OD3j1yN1/4sUFg4D79R2hppAyWeSzrJIvlRkS+sDVheIxATpNrwahEgt4YISCVBhDY4Jl J27t6ty4NjswpOvTlh/PyHXFl1rlHrTON7jv+U9MPRooeZ3KKMThqh/GpuK7h8x4cqaErx q3YsuXVumvv884BGJFN3P0DZWP/15ztRiqXmvrevGE6C6TFfpxXM9v1tQ8Q9yA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1761566547; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=PTSmBUT+NSU0Pf3UvTw6VzFlnJ/x+0CdayRPcxXKwSA=; b=MeOHNcw7TzIiuGD3wOrWsD/l+GyueqjgbN1ud+kBSadmyLfiiuJHqTtErnDRQUF/mA1+hG qwIKJmroMpHgW50CanlzOsIy/m5tzjPT0DIYZWoi70ma2lGITO6ouJX40UJTXw0JysL2iy 1MbBJK8epl0KPlTLUYaz6Y1nuSA3IotUVYuLECEoTHD3wT4f78XL9t5VHQNeeXd3Ony2te EhN+H34ryfjiPBjb0TPLbUpavV+7jqXET6Q42Q3wUtAHy+gSczYnBLVdIACXuCqkDKJE+f f68Xl46nEyE02mOoD/LKLWtxMR3q1JfGhC4gcEj8lsd1zA+XfrFFlpBxaHA2Xw== ARC-Seal: i=1; s=dkim; d=freebsd.org; t=1761566547; a=rsa-sha256; cv=none; b=X8Pvq+bpOOtpi4qN38zIyHCsYRhVLhD3V2VldgamKfomwXRz7HwOragEQl0oQG2RbOE0p3 rofmsgpwGtVShCk4fDjS+KlT392qPoM+khowb55cX2N0aJeqhI9iYli5kdH1wZRHgv+aYW WKXeG23S/eVsTt/840SdXiXDpYYmD25TDo92vR5aHGqn1KBQcD+YYwjjvrAfEH1T5qBhA3 GpI7VU+N5JhKRrqzv/zzxpCaKtExmVLBDFEdH+JDqfUMMoCdwqW1CIpI4vnxbXPyGDxrRJ pkyIran603NmFwkYQBRCDqN4fSqpsVFxu91vQqwtciCZ8sPbK1FdUK21wQF3HQ== ARC-Authentication-Results: i=1; mx1.freebsd.org; none Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 4cwBvl1mvRz1HQy; Mon, 27 Oct 2025 12:02:27 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from gitrepo.freebsd.org ([127.0.1.44]) by gitrepo.freebsd.org (8.18.1/8.18.1) with ESMTP id 59RC2RG6077473; Mon, 27 Oct 2025 12:02:27 GMT (envelope-from git@gitrepo.freebsd.org) Received: (from git@localhost) by gitrepo.freebsd.org (8.18.1/8.18.1/Submit) id 59RC2RBZ077470; Mon, 27 Oct 2025 12:02:27 GMT (envelope-from git) Date: Mon, 27 Oct 2025 12:02:27 GMT Message-Id: <202510271202.59RC2RBZ077470@gitrepo.freebsd.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org From: Andrew Turner Subject: git: b57a571a0019 - main - arm64: Split out accessing special registers List-Id: Commit messages for all branches of the src repository List-Archive: https://lists.freebsd.org/archives/dev-commits-src-all List-Help: List-Post: List-Subscribe: List-Unsubscribe: X-BeenThere: dev-commits-src-all@freebsd.org Sender: owner-dev-commits-src-all@FreeBSD.org MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: andrew X-Git-Repository: src X-Git-Refname: refs/heads/main X-Git-Reftype: branch X-Git-Commit: b57a571a001958febec042e15c571c5074ce44ce Auto-Submitted: auto-generated The branch main has been updated by andrew: URL: https://cgit.FreeBSD.org/src/commit/?id=b57a571a001958febec042e15c571c5074ce44ce commit b57a571a001958febec042e15c571c5074ce44ce Author: Andrew Turner AuthorDate: 2025-10-27 10:56:17 +0000 Commit: Andrew Turner CommitDate: 2025-10-27 11:36:17 +0000 arm64: Split out accessing special registers We shouldn't need to include armreg.h just to access special registers that are not defined in this file. Split out the parts that should be common with arm64.h and hypervisor.h. Reviewed by: emaste Sponsored by: Arm Ltd Differential Revision: https://reviews.freebsd.org/D53324 --- sys/arm64/include/_armreg.h | 56 ++++++++++++++++++++++++++++++++++++++++++ sys/arm64/include/armreg.h | 20 ++------------- sys/arm64/include/hypervisor.h | 2 ++ 3 files changed, 60 insertions(+), 18 deletions(-) diff --git a/sys/arm64/include/_armreg.h b/sys/arm64/include/_armreg.h new file mode 100644 index 000000000000..7aa3c358b327 --- /dev/null +++ b/sys/arm64/include/_armreg.h @@ -0,0 +1,56 @@ +/*- + * Copyright (c) 2013, 2014 Andrew Turner + * Copyright (c) 2015,2021 The FreeBSD Foundation + * + * Portions of this software were developed by Andrew Turner + * under sponsorship from the FreeBSD Foundation. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#if !defined(_MACHINE_ARMREG_H_) && \ + !defined(_MACHINE_HYPERVISOR_H_) +#error Do not include this file directly +#endif + +#ifndef _MACHINE__ARMREG_H_ +#define _MACHINE__ARMREG_H_ + +#define __MRS_REG_ALT_NAME(op0, op1, crn, crm, op2) \ + S##op0##_##op1##_C##crn##_C##crm##_##op2 +#define _MRS_REG_ALT_NAME(op0, op1, crn, crm, op2) \ + __MRS_REG_ALT_NAME(op0, op1, crn, crm, op2) +#define MRS_REG_ALT_NAME(reg) \ + _MRS_REG_ALT_NAME(reg##_op0, reg##_op1, reg##_CRn, reg##_CRm, reg##_op2) + + +#define READ_SPECIALREG(reg) \ +({ uint64_t _val; \ + __asm __volatile("mrs %0, " __STRING(reg) : "=&r" (_val)); \ + _val; \ +}) +#define WRITE_SPECIALREG(reg, _val) \ + __asm __volatile("msr " __STRING(reg) ", %0" : : "r"((uint64_t)_val)) + +#define UL(x) UINT64_C(x) + +#endif /* !_MACHINE__ARMREG_H_ */ diff --git a/sys/arm64/include/armreg.h b/sys/arm64/include/armreg.h index aca3d4c07450..aa9b672ad85a 100644 --- a/sys/arm64/include/armreg.h +++ b/sys/arm64/include/armreg.h @@ -34,25 +34,9 @@ #ifndef _MACHINE_ARMREG_H_ #define _MACHINE_ARMREG_H_ -#define INSN_SIZE 4 - -#define __MRS_REG_ALT_NAME(op0, op1, crn, crm, op2) \ - S##op0##_##op1##_C##crn##_C##crm##_##op2 -#define _MRS_REG_ALT_NAME(op0, op1, crn, crm, op2) \ - __MRS_REG_ALT_NAME(op0, op1, crn, crm, op2) -#define MRS_REG_ALT_NAME(reg) \ - _MRS_REG_ALT_NAME(reg##_op0, reg##_op1, reg##_CRn, reg##_CRm, reg##_op2) - +#include -#define READ_SPECIALREG(reg) \ -({ uint64_t _val; \ - __asm __volatile("mrs %0, " __STRING(reg) : "=&r" (_val)); \ - _val; \ -}) -#define WRITE_SPECIALREG(reg, _val) \ - __asm __volatile("msr " __STRING(reg) ", %0" : : "r"((uint64_t)_val)) - -#define UL(x) UINT64_C(x) +#define INSN_SIZE 4 /* AFSR0_EL1 - Auxiliary Fault Status Register 0 */ #define AFSR0_EL1_REG MRS_REG_ALT_NAME(AFSR0_EL1) diff --git a/sys/arm64/include/hypervisor.h b/sys/arm64/include/hypervisor.h index 8feabd2b981b..7d405e63cd8d 100644 --- a/sys/arm64/include/hypervisor.h +++ b/sys/arm64/include/hypervisor.h @@ -30,6 +30,8 @@ #ifndef _MACHINE_HYPERVISOR_H_ #define _MACHINE_HYPERVISOR_H_ +#include + /* * These registers are only useful when in hypervisor context, * e.g. specific to EL2, or controlling the hypervisor.