Date: Wed, 27 Jun 2018 19:14:09 +0000 (UTC) From: Dimitry Andric <dim@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-vendor@freebsd.org Subject: svn commit: r335720 - in vendor/llvm/dist-release_60: . include/llvm/CodeGen include/llvm/IR lib/Analysis lib/CodeGen lib/ExecutionEngine/RuntimeDyld lib/IR lib/MC lib/Support lib/Target/AArch64 li... Message-ID: <201806271914.w5RJE94Y042787@repo.freebsd.org>
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Author: dim Date: Wed Jun 27 19:14:09 2018 New Revision: 335720 URL: https://svnweb.freebsd.org/changeset/base/335720 Log: Vendor import of llvm 6.0.1 release r335540: https://llvm.org/svn/llvm-project/llvm/tags/RELEASE_601/final@335540 Added: vendor/llvm/dist-release_60/lib/Target/X86/X86FlagsCopyLowering.cpp (contents, props changed) vendor/llvm/dist-release_60/test/Analysis/MemorySSA/pr36883.ll vendor/llvm/dist-release_60/test/CodeGen/AArch64/inlineasm-S-constraint.ll vendor/llvm/dist-release_60/test/CodeGen/AArch64/spill-stack-realignment.mir vendor/llvm/dist-release_60/test/CodeGen/AMDGPU/ctpop16.ll vendor/llvm/dist-release_60/test/CodeGen/Hexagon/ifcvt-diamond-ret.mir vendor/llvm/dist-release_60/test/CodeGen/MIR/PowerPC/ifcvt-diamond-ret.mir vendor/llvm/dist-release_60/test/CodeGen/Mips/indirect-jump-hazard/ vendor/llvm/dist-release_60/test/CodeGen/Mips/indirect-jump-hazard/calls.ll vendor/llvm/dist-release_60/test/CodeGen/Mips/indirect-jump-hazard/guards-verify-call.mir vendor/llvm/dist-release_60/test/CodeGen/Mips/indirect-jump-hazard/guards-verify-tailcall.mir vendor/llvm/dist-release_60/test/CodeGen/Mips/indirect-jump-hazard/jumptables.ll vendor/llvm/dist-release_60/test/CodeGen/Mips/indirect-jump-hazard/long-branch.ll vendor/llvm/dist-release_60/test/CodeGen/Mips/indirect-jump-hazard/long-calls.ll vendor/llvm/dist-release_60/test/CodeGen/Mips/indirect-jump-hazard/unsupported-micromips.ll vendor/llvm/dist-release_60/test/CodeGen/Mips/indirect-jump-hazard/unsupported-mips32.ll vendor/llvm/dist-release_60/test/CodeGen/Mips/inlineasm-cnstrnt-bad-l1.ll vendor/llvm/dist-release_60/test/CodeGen/PowerPC/no-dup-of-bdnz.ll vendor/llvm/dist-release_60/test/CodeGen/PowerPC/pr35402.ll vendor/llvm/dist-release_60/test/CodeGen/Thumb/PR36658.mir vendor/llvm/dist-release_60/test/CodeGen/X86/domain-reassignment-implicit-def.ll vendor/llvm/dist-release_60/test/CodeGen/X86/domain-reassignment-test.ll vendor/llvm/dist-release_60/test/CodeGen/X86/flags-copy-lowering.mir vendor/llvm/dist-release_60/test/CodeGen/X86/pr37264.ll vendor/llvm/dist-release_60/test/DebugInfo/X86/live-debug-vars-discard-invalid.mir vendor/llvm/dist-release_60/test/ExecutionEngine/RuntimeDyld/PowerPC/Inputs/ vendor/llvm/dist-release_60/test/ExecutionEngine/RuntimeDyld/PowerPC/Inputs/ppc64_elf_module_b.s (contents, props changed) vendor/llvm/dist-release_60/test/ExecutionEngine/RuntimeDyld/PowerPC/ppc64_elf.s (contents, props changed) vendor/llvm/dist-release_60/test/MC/Mips/unsupported-relocation.s (contents, props changed) vendor/llvm/dist-release_60/test/Transforms/ArgumentPromotion/musttail.ll vendor/llvm/dist-release_60/test/Transforms/CallSiteSplitting/musttail.ll vendor/llvm/dist-release_60/test/Transforms/DeadArgElim/musttail-caller.ll vendor/llvm/dist-release_60/test/Transforms/GlobalOpt/musttail_cc.ll vendor/llvm/dist-release_60/test/Transforms/IPConstantProp/musttail-call.ll vendor/llvm/dist-release_60/test/Transforms/JumpThreading/header-succ.ll vendor/llvm/dist-release_60/test/Transforms/MergeFunc/inline-asm.ll vendor/llvm/dist-release_60/test/Transforms/MergeFunc/weak-small.ll Deleted: vendor/llvm/dist-release_60/test/CodeGen/X86/clobber-fi0.ll vendor/llvm/dist-release_60/test/CodeGen/X86/eflags-copy-expansion.mir Modified: vendor/llvm/dist-release_60/CMakeLists.txt vendor/llvm/dist-release_60/include/llvm/CodeGen/MachineBasicBlock.h vendor/llvm/dist-release_60/include/llvm/CodeGen/TargetInstrInfo.h vendor/llvm/dist-release_60/include/llvm/IR/IntrinsicsPowerPC.td vendor/llvm/dist-release_60/lib/Analysis/GlobalsModRef.cpp vendor/llvm/dist-release_60/lib/Analysis/MemorySSA.cpp vendor/llvm/dist-release_60/lib/CodeGen/IfConversion.cpp vendor/llvm/dist-release_60/lib/CodeGen/LiveDebugVariables.cpp vendor/llvm/dist-release_60/lib/CodeGen/MachineBasicBlock.cpp vendor/llvm/dist-release_60/lib/CodeGen/MachineBlockPlacement.cpp vendor/llvm/dist-release_60/lib/CodeGen/PeepholeOptimizer.cpp vendor/llvm/dist-release_60/lib/CodeGen/TargetInstrInfo.cpp vendor/llvm/dist-release_60/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp vendor/llvm/dist-release_60/lib/IR/Core.cpp vendor/llvm/dist-release_60/lib/MC/MCObjectFileInfo.cpp vendor/llvm/dist-release_60/lib/Support/CMakeLists.txt vendor/llvm/dist-release_60/lib/Support/Host.cpp vendor/llvm/dist-release_60/lib/Target/AArch64/AArch64AsmPrinter.cpp vendor/llvm/dist-release_60/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp vendor/llvm/dist-release_60/lib/Target/AArch64/AArch64FrameLowering.cpp vendor/llvm/dist-release_60/lib/Target/AArch64/AArch64ISelLowering.cpp vendor/llvm/dist-release_60/lib/Target/AArch64/AArch64InstrInfo.td vendor/llvm/dist-release_60/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp vendor/llvm/dist-release_60/lib/Target/AMDGPU/SIISelLowering.cpp vendor/llvm/dist-release_60/lib/Target/AMDGPU/SIInstructions.td vendor/llvm/dist-release_60/lib/Target/ARM/ARMBaseInstrInfo.cpp vendor/llvm/dist-release_60/lib/Target/ARM/ARMComputeBlockSize.cpp vendor/llvm/dist-release_60/lib/Target/Mips/AsmParser/MipsAsmParser.cpp vendor/llvm/dist-release_60/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp vendor/llvm/dist-release_60/lib/Target/Mips/MicroMips32r6InstrInfo.td vendor/llvm/dist-release_60/lib/Target/Mips/MicroMipsInstrInfo.td vendor/llvm/dist-release_60/lib/Target/Mips/Mips.td vendor/llvm/dist-release_60/lib/Target/Mips/Mips32r6InstrInfo.td vendor/llvm/dist-release_60/lib/Target/Mips/Mips64InstrInfo.td vendor/llvm/dist-release_60/lib/Target/Mips/Mips64r6InstrInfo.td vendor/llvm/dist-release_60/lib/Target/Mips/MipsDSPInstrFormats.td vendor/llvm/dist-release_60/lib/Target/Mips/MipsFastISel.cpp vendor/llvm/dist-release_60/lib/Target/Mips/MipsISelLowering.cpp vendor/llvm/dist-release_60/lib/Target/Mips/MipsInstrFormats.td vendor/llvm/dist-release_60/lib/Target/Mips/MipsInstrInfo.cpp vendor/llvm/dist-release_60/lib/Target/Mips/MipsInstrInfo.td vendor/llvm/dist-release_60/lib/Target/Mips/MipsLongBranch.cpp vendor/llvm/dist-release_60/lib/Target/Mips/MipsSEISelLowering.cpp vendor/llvm/dist-release_60/lib/Target/Mips/MipsSubtarget.cpp vendor/llvm/dist-release_60/lib/Target/Mips/MipsSubtarget.h vendor/llvm/dist-release_60/lib/Target/NVPTX/NVPTXTargetMachine.cpp vendor/llvm/dist-release_60/lib/Target/PowerPC/PPCISelLowering.cpp vendor/llvm/dist-release_60/lib/Target/PowerPC/PPCInstrInfo.cpp vendor/llvm/dist-release_60/lib/Target/X86/CMakeLists.txt vendor/llvm/dist-release_60/lib/Target/X86/Disassembler/X86Disassembler.cpp vendor/llvm/dist-release_60/lib/Target/X86/X86.h vendor/llvm/dist-release_60/lib/Target/X86/X86DomainReassignment.cpp vendor/llvm/dist-release_60/lib/Target/X86/X86FastISel.cpp vendor/llvm/dist-release_60/lib/Target/X86/X86ISelLowering.cpp vendor/llvm/dist-release_60/lib/Target/X86/X86ISelLowering.h vendor/llvm/dist-release_60/lib/Target/X86/X86InstrArithmetic.td vendor/llvm/dist-release_60/lib/Target/X86/X86InstrCompiler.td vendor/llvm/dist-release_60/lib/Target/X86/X86InstrInfo.cpp vendor/llvm/dist-release_60/lib/Target/X86/X86InstrInfo.h vendor/llvm/dist-release_60/lib/Target/X86/X86InstrInfo.td vendor/llvm/dist-release_60/lib/Target/X86/X86InstrSystem.td vendor/llvm/dist-release_60/lib/Target/X86/X86RegisterInfo.td vendor/llvm/dist-release_60/lib/Target/X86/X86Schedule.td vendor/llvm/dist-release_60/lib/Target/X86/X86ScheduleAtom.td vendor/llvm/dist-release_60/lib/Target/X86/X86TargetMachine.cpp vendor/llvm/dist-release_60/lib/Transforms/IPO/ArgumentPromotion.cpp vendor/llvm/dist-release_60/lib/Transforms/IPO/DeadArgumentElimination.cpp vendor/llvm/dist-release_60/lib/Transforms/IPO/GlobalOpt.cpp vendor/llvm/dist-release_60/lib/Transforms/IPO/MergeFunctions.cpp vendor/llvm/dist-release_60/lib/Transforms/InstCombine/InstructionCombining.cpp vendor/llvm/dist-release_60/lib/Transforms/Scalar/CallSiteSplitting.cpp vendor/llvm/dist-release_60/lib/Transforms/Scalar/DivRemPairs.cpp vendor/llvm/dist-release_60/lib/Transforms/Scalar/JumpThreading.cpp vendor/llvm/dist-release_60/lib/Transforms/Scalar/SCCP.cpp vendor/llvm/dist-release_60/lib/Transforms/Utils/FunctionComparator.cpp vendor/llvm/dist-release_60/test/CodeGen/AArch64/arm64-indexed-vector-ldst-2.ll vendor/llvm/dist-release_60/test/CodeGen/AArch64/arm64-zero-cycle-zeroing.ll vendor/llvm/dist-release_60/test/CodeGen/AArch64/falkor-hwpf-fix.mir vendor/llvm/dist-release_60/test/CodeGen/ARM/peephole-phi.mir vendor/llvm/dist-release_60/test/CodeGen/Mips/const-mult.ll vendor/llvm/dist-release_60/test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll vendor/llvm/dist-release_60/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir vendor/llvm/dist-release_60/test/CodeGen/X86/GlobalISel/add-scalar.ll vendor/llvm/dist-release_60/test/CodeGen/X86/O0-pipeline.ll vendor/llvm/dist-release_60/test/CodeGen/X86/cmpxchg-clobber-flags.ll vendor/llvm/dist-release_60/test/CodeGen/X86/copy-eflags.ll vendor/llvm/dist-release_60/test/CodeGen/X86/fast-isel-shift.ll vendor/llvm/dist-release_60/test/CodeGen/X86/ipra-reg-usage.ll vendor/llvm/dist-release_60/test/CodeGen/X86/mul-i1024.ll vendor/llvm/dist-release_60/test/CodeGen/X86/peephole-na-phys-copy-folding.ll vendor/llvm/dist-release_60/test/CodeGen/X86/win64_frame.ll vendor/llvm/dist-release_60/test/CodeGen/X86/x86-repmov-copy-eflags.ll vendor/llvm/dist-release_60/test/DebugInfo/X86/dbg-value-inlined-parameter.ll vendor/llvm/dist-release_60/test/MC/ELF/cfi-large-model.s vendor/llvm/dist-release_60/test/Transforms/InstCombine/gep-addrspace.ll vendor/llvm/dist-release_60/tools/llvm-config/CMakeLists.txt Modified: vendor/llvm/dist-release_60/CMakeLists.txt ============================================================================== --- vendor/llvm/dist-release_60/CMakeLists.txt Wed Jun 27 19:10:32 2018 (r335719) +++ vendor/llvm/dist-release_60/CMakeLists.txt Wed Jun 27 19:14:09 2018 (r335720) @@ -24,7 +24,7 @@ if(NOT DEFINED LLVM_VERSION_MINOR) set(LLVM_VERSION_MINOR 0) endif() if(NOT DEFINED LLVM_VERSION_PATCH) - set(LLVM_VERSION_PATCH 0) + set(LLVM_VERSION_PATCH 1) endif() if(NOT DEFINED LLVM_VERSION_SUFFIX) set(LLVM_VERSION_SUFFIX "") Modified: vendor/llvm/dist-release_60/include/llvm/CodeGen/MachineBasicBlock.h ============================================================================== --- vendor/llvm/dist-release_60/include/llvm/CodeGen/MachineBasicBlock.h Wed Jun 27 19:10:32 2018 (r335719) +++ vendor/llvm/dist-release_60/include/llvm/CodeGen/MachineBasicBlock.h Wed Jun 27 19:14:09 2018 (r335720) @@ -449,6 +449,13 @@ class MachineBasicBlock (public) /// Replace successor OLD with NEW and update probability info. void replaceSuccessor(MachineBasicBlock *Old, MachineBasicBlock *New); + /// Copy a successor (and any probability info) from original block to this + /// block's. Uses an iterator into the original blocks successors. + /// + /// This is useful when doing a partial clone of successors. Afterward, the + /// probabilities may need to be normalized. + void copySuccessor(MachineBasicBlock *Orig, succ_iterator I); + /// Transfers all the successors from MBB to this machine basic block (i.e., /// copies all the successors FromMBB and remove all the successors from /// FromMBB). Modified: vendor/llvm/dist-release_60/include/llvm/CodeGen/TargetInstrInfo.h ============================================================================== --- vendor/llvm/dist-release_60/include/llvm/CodeGen/TargetInstrInfo.h Wed Jun 27 19:10:32 2018 (r335719) +++ vendor/llvm/dist-release_60/include/llvm/CodeGen/TargetInstrInfo.h Wed Jun 27 19:14:09 2018 (r335720) @@ -421,7 +421,8 @@ class TargetInstrInfo : public MCInstrInfo { (public) /// Build the equivalent inputs of a REG_SEQUENCE for the given \p MI /// and \p DefIdx. /// \p [out] InputRegs of the equivalent REG_SEQUENCE. Each element of - /// the list is modeled as <Reg:SubReg, SubIdx>. + /// the list is modeled as <Reg:SubReg, SubIdx>. Operands with the undef + /// flag are not added to this list. /// E.g., REG_SEQUENCE %1:sub1, sub0, %2, sub1 would produce /// two elements: /// - %1:sub1, sub0 @@ -446,7 +447,8 @@ class TargetInstrInfo : public MCInstrInfo { (public) /// - %1:sub1, sub0 /// /// \returns true if it is possible to build such an input sequence - /// with the pair \p MI, \p DefIdx. False otherwise. + /// with the pair \p MI, \p DefIdx and the operand has no undef flag set. + /// False otherwise. /// /// \pre MI.isExtractSubreg() or MI.isExtractSubregLike(). /// @@ -465,7 +467,8 @@ class TargetInstrInfo : public MCInstrInfo { (public) /// - InsertedReg: %1:sub1, sub3 /// /// \returns true if it is possible to build such an input sequence - /// with the pair \p MI, \p DefIdx. False otherwise. + /// with the pair \p MI, \p DefIdx and the operand has no undef flag set. + /// False otherwise. /// /// \pre MI.isInsertSubreg() or MI.isInsertSubregLike(). /// Modified: vendor/llvm/dist-release_60/include/llvm/IR/IntrinsicsPowerPC.td ============================================================================== --- vendor/llvm/dist-release_60/include/llvm/IR/IntrinsicsPowerPC.td Wed Jun 27 19:10:32 2018 (r335719) +++ vendor/llvm/dist-release_60/include/llvm/IR/IntrinsicsPowerPC.td Wed Jun 27 19:14:09 2018 (r335720) @@ -36,8 +36,12 @@ let TargetPrefix = "ppc" in { // All intrinsics start // Intrinsics used to generate ctr-based loops. These should only be // generated by the PowerPC backend! + // The branch intrinsic is marked as NoDuplicate because loop rotation will + // attempt to duplicate it forming loops where a block reachable from one + // instance of it can contain another. def int_ppc_mtctr : Intrinsic<[], [llvm_anyint_ty], []>; - def int_ppc_is_decremented_ctr_nonzero : Intrinsic<[llvm_i1_ty], [], []>; + def int_ppc_is_decremented_ctr_nonzero : + Intrinsic<[llvm_i1_ty], [], [IntrNoDuplicate]>; // Intrinsics for [double]word extended forms of divide instructions def int_ppc_divwe : GCCBuiltin<"__builtin_divwe">, Modified: vendor/llvm/dist-release_60/lib/Analysis/GlobalsModRef.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/Analysis/GlobalsModRef.cpp Wed Jun 27 19:10:32 2018 (r335719) +++ vendor/llvm/dist-release_60/lib/Analysis/GlobalsModRef.cpp Wed Jun 27 19:14:09 2018 (r335720) @@ -502,6 +502,8 @@ void GlobalsAAResult::AnalyzeCallGraph(CallGraph &CG, } FunctionInfo &FI = FunctionInfos[F]; + Handles.emplace_front(*this, F); + Handles.front().I = Handles.begin(); bool KnowNothing = false; // Collect the mod/ref properties due to called functions. We only compute Modified: vendor/llvm/dist-release_60/lib/Analysis/MemorySSA.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/Analysis/MemorySSA.cpp Wed Jun 27 19:10:32 2018 (r335719) +++ vendor/llvm/dist-release_60/lib/Analysis/MemorySSA.cpp Wed Jun 27 19:14:09 2018 (r335720) @@ -153,9 +153,14 @@ class MemoryLocOrCall { (public) if (IsCall != Other.IsCall) return false; - if (IsCall) - return CS.getCalledValue() == Other.CS.getCalledValue(); - return Loc == Other.Loc; + if (!IsCall) + return Loc == Other.Loc; + + if (CS.getCalledValue() != Other.CS.getCalledValue()) + return false; + + return CS.arg_size() == Other.CS.arg_size() && + std::equal(CS.arg_begin(), CS.arg_end(), Other.CS.arg_begin()); } private: @@ -179,12 +184,18 @@ template <> struct DenseMapInfo<MemoryLocOrCall> { } static unsigned getHashValue(const MemoryLocOrCall &MLOC) { - if (MLOC.IsCall) - return hash_combine(MLOC.IsCall, - DenseMapInfo<const Value *>::getHashValue( - MLOC.getCS().getCalledValue())); - return hash_combine( - MLOC.IsCall, DenseMapInfo<MemoryLocation>::getHashValue(MLOC.getLoc())); + if (!MLOC.IsCall) + return hash_combine( + MLOC.IsCall, + DenseMapInfo<MemoryLocation>::getHashValue(MLOC.getLoc())); + + hash_code hash = + hash_combine(MLOC.IsCall, DenseMapInfo<const Value *>::getHashValue( + MLOC.getCS().getCalledValue())); + + for (const Value *Arg : MLOC.getCS().args()) + hash = hash_combine(hash, DenseMapInfo<const Value *>::getHashValue(Arg)); + return hash; } static bool isEqual(const MemoryLocOrCall &LHS, const MemoryLocOrCall &RHS) { Modified: vendor/llvm/dist-release_60/lib/CodeGen/IfConversion.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/CodeGen/IfConversion.cpp Wed Jun 27 19:10:32 2018 (r335719) +++ vendor/llvm/dist-release_60/lib/CodeGen/IfConversion.cpp Wed Jun 27 19:14:09 2018 (r335720) @@ -1714,20 +1714,25 @@ bool IfConverter::IfConvertDiamondCommon( } // Remove the duplicated instructions at the beginnings of both paths. - // Skip dbg_value instructions + // Skip dbg_value instructions. MachineBasicBlock::iterator DI1 = MBB1.getFirstNonDebugInstr(); MachineBasicBlock::iterator DI2 = MBB2.getFirstNonDebugInstr(); BBI1->NonPredSize -= NumDups1; BBI2->NonPredSize -= NumDups1; // Skip past the dups on each side separately since there may be - // differing dbg_value entries. + // differing dbg_value entries. NumDups1 can include a "return" + // instruction, if it's not marked as "branch". for (unsigned i = 0; i < NumDups1; ++DI1) { + if (DI1 == MBB1.end()) + break; if (!DI1->isDebugValue()) ++i; } while (NumDups1 != 0) { ++DI2; + if (DI2 == MBB2.end()) + break; if (!DI2->isDebugValue()) --NumDups1; } @@ -1738,11 +1743,16 @@ bool IfConverter::IfConvertDiamondCommon( Redefs.stepForward(MI, Dummy); } } + BBI.BB->splice(BBI.BB->end(), &MBB1, MBB1.begin(), DI1); MBB2.erase(MBB2.begin(), DI2); - // The branches have been checked to match, so it is safe to remove the branch - // in BB1 and rely on the copy in BB2 + // The branches have been checked to match, so it is safe to remove the + // branch in BB1 and rely on the copy in BB2. The complication is that + // the blocks may end with a return instruction, which may or may not + // be marked as "branch". If it's not, then it could be included in + // "dups1", leaving the blocks potentially empty after moving the common + // duplicates. #ifndef NDEBUG // Unanalyzable branches must match exactly. Check that now. if (!BBI1->IsBrAnalyzable) @@ -1768,11 +1778,14 @@ bool IfConverter::IfConvertDiamondCommon( if (RemoveBranch) BBI2->NonPredSize -= TII->removeBranch(*BBI2->BB); else { - do { - assert(DI2 != MBB2.begin()); - DI2--; - } while (DI2->isBranch() || DI2->isDebugValue()); - DI2++; + // Make DI2 point to the end of the range where the common "tail" + // instructions could be found. + while (DI2 != MBB2.begin()) { + MachineBasicBlock::iterator Prev = std::prev(DI2); + if (!Prev->isBranch() && !Prev->isDebugValue()) + break; + DI2 = Prev; + } } while (NumDups2 != 0) { // NumDups2 only counted non-dbg_value instructions, so this won't @@ -1833,11 +1846,15 @@ bool IfConverter::IfConvertDiamondCommon( // a non-predicated in BBI2, then we don't want to predicate the one from // BBI2. The reason is that if we merged these blocks, we would end up with // two predicated terminators in the same block. + // Also, if the branches in MBB1 and MBB2 were non-analyzable, then don't + // predicate them either. They were checked to be identical, and so the + // same branch would happen regardless of which path was taken. if (!MBB2.empty() && (DI2 == MBB2.end())) { MachineBasicBlock::iterator BBI1T = MBB1.getFirstTerminator(); MachineBasicBlock::iterator BBI2T = MBB2.getFirstTerminator(); - if (BBI1T != MBB1.end() && TII->isPredicated(*BBI1T) && - BBI2T != MBB2.end() && !TII->isPredicated(*BBI2T)) + bool BB1Predicated = BBI1T != MBB1.end() && TII->isPredicated(*BBI1T); + bool BB2NonPredicated = BBI2T != MBB2.end() && !TII->isPredicated(*BBI2T); + if (BB2NonPredicated && (BB1Predicated || !BBI2->IsBrAnalyzable)) --DI2; } Modified: vendor/llvm/dist-release_60/lib/CodeGen/LiveDebugVariables.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/CodeGen/LiveDebugVariables.cpp Wed Jun 27 19:10:32 2018 (r335719) +++ vendor/llvm/dist-release_60/lib/CodeGen/LiveDebugVariables.cpp Wed Jun 27 19:14:09 2018 (r335720) @@ -514,6 +514,39 @@ bool LDVImpl::handleDebugValue(MachineInstr &MI, SlotI return false; } + // Detect invalid DBG_VALUE instructions, with a debug-use of a virtual + // register that hasn't been defined yet. If we do not remove those here, then + // the re-insertion of the DBG_VALUE instruction after register allocation + // will be incorrect. + // TODO: If earlier passes are corrected to generate sane debug information + // (and if the machine verifier is improved to catch this), then these checks + // could be removed or replaced by asserts. + bool Discard = false; + if (MI.getOperand(0).isReg() && + TargetRegisterInfo::isVirtualRegister(MI.getOperand(0).getReg())) { + const unsigned Reg = MI.getOperand(0).getReg(); + if (!LIS->hasInterval(Reg)) { + // The DBG_VALUE is described by a virtual register that does not have a + // live interval. Discard the DBG_VALUE. + Discard = true; + DEBUG(dbgs() << "Discarding debug info (no LIS interval): " + << Idx << " " << MI); + } else { + // The DBG_VALUE is only valid if either Reg is live out from Idx, or Reg + // is defined dead at Idx (where Idx is the slot index for the instruction + // preceeding the DBG_VALUE). + const LiveInterval &LI = LIS->getInterval(Reg); + LiveQueryResult LRQ = LI.Query(Idx); + if (!LRQ.valueOutOrDead()) { + // We have found a DBG_VALUE with the value in a virtual register that + // is not live. Discard the DBG_VALUE. + Discard = true; + DEBUG(dbgs() << "Discarding debug info (reg not live): " + << Idx << " " << MI); + } + } + } + // Get or create the UserValue for (variable,offset) here. bool IsIndirect = MI.getOperand(1).isImm(); if (IsIndirect) @@ -522,7 +555,13 @@ bool LDVImpl::handleDebugValue(MachineInstr &MI, SlotI const DIExpression *Expr = MI.getDebugExpression(); UserValue *UV = getUserValue(Var, Expr, MI.getDebugLoc()); - UV->addDef(Idx, MI.getOperand(0), IsIndirect); + if (!Discard) + UV->addDef(Idx, MI.getOperand(0), IsIndirect); + else { + MachineOperand MO = MachineOperand::CreateReg(0U, false); + MO.setIsDebug(); + UV->addDef(Idx, MO, false); + } return true; } Modified: vendor/llvm/dist-release_60/lib/CodeGen/MachineBasicBlock.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/CodeGen/MachineBasicBlock.cpp Wed Jun 27 19:10:32 2018 (r335719) +++ vendor/llvm/dist-release_60/lib/CodeGen/MachineBasicBlock.cpp Wed Jun 27 19:14:09 2018 (r335720) @@ -646,6 +646,14 @@ void MachineBasicBlock::replaceSuccessor(MachineBasicB removeSuccessor(OldI); } +void MachineBasicBlock::copySuccessor(MachineBasicBlock *Orig, + succ_iterator I) { + if (Orig->Probs.empty()) + addSuccessor(*I, Orig->getSuccProbability(I)); + else + addSuccessorWithoutProb(*I); +} + void MachineBasicBlock::addPredecessor(MachineBasicBlock *Pred) { Predecessors.push_back(Pred); } Modified: vendor/llvm/dist-release_60/lib/CodeGen/MachineBlockPlacement.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/CodeGen/MachineBlockPlacement.cpp Wed Jun 27 19:10:32 2018 (r335719) +++ vendor/llvm/dist-release_60/lib/CodeGen/MachineBlockPlacement.cpp Wed Jun 27 19:14:09 2018 (r335720) @@ -513,6 +513,11 @@ class MachineBlockPlacement : public MachineFunctionPa bool runOnMachineFunction(MachineFunction &F) override; + bool allowTailDupPlacement() const { + assert(F); + return TailDupPlacement && !F->getTarget().requiresStructuredCFG(); + } + void getAnalysisUsage(AnalysisUsage &AU) const override { AU.addRequired<MachineBranchProbabilityInfo>(); AU.addRequired<MachineBlockFrequencyInfo>(); @@ -1018,7 +1023,7 @@ MachineBlockPlacement::getBestTrellisSuccessor( MachineBasicBlock *Succ1 = BestA.Dest; MachineBasicBlock *Succ2 = BestB.Dest; // Check to see if tail-duplication would be profitable. - if (TailDupPlacement && shouldTailDuplicate(Succ2) && + if (allowTailDupPlacement() && shouldTailDuplicate(Succ2) && canTailDuplicateUnplacedPreds(BB, Succ2, Chain, BlockFilter) && isProfitableToTailDup(BB, Succ2, MBPI->getEdgeProbability(BB, Succ1), Chain, BlockFilter)) { @@ -1044,7 +1049,7 @@ MachineBlockPlacement::getBestTrellisSuccessor( return Result; } -/// When the option TailDupPlacement is on, this method checks if the +/// When the option allowTailDupPlacement() is on, this method checks if the /// fallthrough candidate block \p Succ (of block \p BB) can be tail-duplicated /// into all of its unplaced, unfiltered predecessors, that are not BB. bool MachineBlockPlacement::canTailDuplicateUnplacedPreds( @@ -1493,7 +1498,7 @@ MachineBlockPlacement::selectBestSuccessor( if (hasBetterLayoutPredecessor(BB, Succ, SuccChain, SuccProb, RealSuccProb, Chain, BlockFilter)) { // If tail duplication would make Succ profitable, place it. - if (TailDupPlacement && shouldTailDuplicate(Succ)) + if (allowTailDupPlacement() && shouldTailDuplicate(Succ)) DupCandidates.push_back(std::make_tuple(SuccProb, Succ)); continue; } @@ -1702,7 +1707,7 @@ void MachineBlockPlacement::buildChain( auto Result = selectBestSuccessor(BB, Chain, BlockFilter); MachineBasicBlock* BestSucc = Result.BB; bool ShouldTailDup = Result.ShouldTailDup; - if (TailDupPlacement) + if (allowTailDupPlacement()) ShouldTailDup |= (BestSucc && shouldTailDuplicate(BestSucc)); // If an immediate successor isn't available, look for the best viable @@ -1724,7 +1729,7 @@ void MachineBlockPlacement::buildChain( // Placement may have changed tail duplication opportunities. // Check for that now. - if (TailDupPlacement && BestSucc && ShouldTailDup) { + if (allowTailDupPlacement() && BestSucc && ShouldTailDup) { // If the chosen successor was duplicated into all its predecessors, // don't bother laying it out, just go round the loop again with BB as // the chain end. @@ -2758,7 +2763,7 @@ bool MachineBlockPlacement::runOnMachineFunction(Machi TailDupSize = TailDupPlacementAggressiveThreshold; } - if (TailDupPlacement) { + if (allowTailDupPlacement()) { MPDT = &getAnalysis<MachinePostDominatorTree>(); if (MF.getFunction().optForSize()) TailDupSize = 1; Modified: vendor/llvm/dist-release_60/lib/CodeGen/PeepholeOptimizer.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/CodeGen/PeepholeOptimizer.cpp Wed Jun 27 19:10:32 2018 (r335719) +++ vendor/llvm/dist-release_60/lib/CodeGen/PeepholeOptimizer.cpp Wed Jun 27 19:14:09 2018 (r335720) @@ -1882,6 +1882,8 @@ ValueTrackerResult ValueTracker::getNextSourceFromCopy return ValueTrackerResult(); // Otherwise, we want the whole source. const MachineOperand &Src = Def->getOperand(1); + if (Src.isUndef()) + return ValueTrackerResult(); return ValueTrackerResult(Src.getReg(), Src.getSubReg()); } @@ -1925,6 +1927,8 @@ ValueTrackerResult ValueTracker::getNextSourceFromBitc } const MachineOperand &Src = Def->getOperand(SrcIdx); + if (Src.isUndef()) + return ValueTrackerResult(); return ValueTrackerResult(Src.getReg(), Src.getSubReg()); } @@ -2093,6 +2097,10 @@ ValueTrackerResult ValueTracker::getNextSourceFromPHI( for (unsigned i = 1, e = Def->getNumOperands(); i < e; i += 2) { auto &MO = Def->getOperand(i); assert(MO.isReg() && "Invalid PHI instruction"); + // We have no code to deal with undef operands. They shouldn't happen in + // normal programs anyway. + if (MO.isUndef()) + return ValueTrackerResult(); Res.addSource(MO.getReg(), MO.getSubReg()); } @@ -2149,9 +2157,14 @@ ValueTrackerResult ValueTracker::getNextSource() { // If we can still move up in the use-def chain, move to the next // definition. if (!TargetRegisterInfo::isPhysicalRegister(Reg) && OneRegSrc) { - Def = MRI.getVRegDef(Reg); - DefIdx = MRI.def_begin(Reg).getOperandNo(); - DefSubReg = Res.getSrcSubReg(0); + MachineRegisterInfo::def_iterator DI = MRI.def_begin(Reg); + if (DI != MRI.def_end()) { + Def = DI->getParent(); + DefIdx = DI.getOperandNo(); + DefSubReg = Res.getSrcSubReg(0); + } else { + Def = nullptr; + } return Res; } } Modified: vendor/llvm/dist-release_60/lib/CodeGen/TargetInstrInfo.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/CodeGen/TargetInstrInfo.cpp Wed Jun 27 19:10:32 2018 (r335719) +++ vendor/llvm/dist-release_60/lib/CodeGen/TargetInstrInfo.cpp Wed Jun 27 19:14:09 2018 (r335720) @@ -1151,6 +1151,8 @@ bool TargetInstrInfo::getRegSequenceInputs( for (unsigned OpIdx = 1, EndOpIdx = MI.getNumOperands(); OpIdx != EndOpIdx; OpIdx += 2) { const MachineOperand &MOReg = MI.getOperand(OpIdx); + if (MOReg.isUndef()) + continue; const MachineOperand &MOSubIdx = MI.getOperand(OpIdx + 1); assert(MOSubIdx.isImm() && "One of the subindex of the reg_sequence is not an immediate"); @@ -1174,6 +1176,8 @@ bool TargetInstrInfo::getExtractSubregInputs( // Def = EXTRACT_SUBREG v0.sub1, sub0. assert(DefIdx == 0 && "EXTRACT_SUBREG only has one def"); const MachineOperand &MOReg = MI.getOperand(1); + if (MOReg.isUndef()) + return false; const MachineOperand &MOSubIdx = MI.getOperand(2); assert(MOSubIdx.isImm() && "The subindex of the extract_subreg is not an immediate"); @@ -1198,6 +1202,8 @@ bool TargetInstrInfo::getInsertSubregInputs( assert(DefIdx == 0 && "INSERT_SUBREG only has one def"); const MachineOperand &MOBaseReg = MI.getOperand(1); const MachineOperand &MOInsertedReg = MI.getOperand(2); + if (MOInsertedReg.isUndef()) + return false; const MachineOperand &MOSubIdx = MI.getOperand(3); assert(MOSubIdx.isImm() && "One of the subindex of the reg_sequence is not an immediate"); Modified: vendor/llvm/dist-release_60/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp Wed Jun 27 19:10:32 2018 (r335719) +++ vendor/llvm/dist-release_60/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp Wed Jun 27 19:14:09 2018 (r335720) @@ -1422,7 +1422,8 @@ RuntimeDyldELF::processRelocationRef( SectionEntry &Section = Sections[SectionID]; uint8_t *Target = Section.getAddressWithOffset(Offset); bool RangeOverflow = false; - if (!Value.SymbolName && SymType != SymbolRef::ST_Unknown) { + bool IsExtern = Value.SymbolName || SymType == SymbolRef::ST_Unknown; + if (!IsExtern) { if (AbiVariant != 2) { // In the ELFv1 ABI, a function call may point to the .opd entry, // so the final symbol value is calculated based on the relocation @@ -1432,21 +1433,24 @@ RuntimeDyldELF::processRelocationRef( } else { // In the ELFv2 ABI, a function symbol may provide a local entry // point, which must be used for direct calls. - uint8_t SymOther = Symbol->getOther(); - Value.Addend += ELF::decodePPC64LocalEntryOffset(SymOther); + if (Value.SectionID == SectionID){ + uint8_t SymOther = Symbol->getOther(); + Value.Addend += ELF::decodePPC64LocalEntryOffset(SymOther); + } } uint8_t *RelocTarget = Sections[Value.SectionID].getAddressWithOffset(Value.Addend); int64_t delta = static_cast<int64_t>(Target - RelocTarget); // If it is within 26-bits branch range, just set the branch target - if (SignExtend64<26>(delta) == delta) { + if (SignExtend64<26>(delta) != delta) { + RangeOverflow = true; + } else if ((AbiVariant != 2) || + (AbiVariant == 2 && Value.SectionID == SectionID)) { RelocationEntry RE(SectionID, Offset, RelType, Value.Addend); addRelocationForSection(RE, Value.SectionID); - } else { - RangeOverflow = true; } } - if (Value.SymbolName || SymType == SymbolRef::ST_Unknown || + if (IsExtern || (AbiVariant == 2 && Value.SectionID != SectionID) || RangeOverflow) { // It is an external symbol (either Value.SymbolName is set, or // SymType is SymbolRef::ST_Unknown) or out of range. @@ -1503,10 +1507,10 @@ RuntimeDyldELF::processRelocationRef( RelType, 0); Section.advanceStubOffset(getMaxStubSize()); } - if (Value.SymbolName || SymType == SymbolRef::ST_Unknown) { + if (IsExtern || (AbiVariant == 2 && Value.SectionID != SectionID)) { // Restore the TOC for external calls if (AbiVariant == 2) - writeInt32BE(Target + 4, 0xE8410018); // ld r2,28(r1) + writeInt32BE(Target + 4, 0xE8410018); // ld r2,24(r1) else writeInt32BE(Target + 4, 0xE8410028); // ld r2,40(r1) } Modified: vendor/llvm/dist-release_60/lib/IR/Core.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/IR/Core.cpp Wed Jun 27 19:10:32 2018 (r335719) +++ vendor/llvm/dist-release_60/lib/IR/Core.cpp Wed Jun 27 19:14:09 2018 (r335720) @@ -359,11 +359,9 @@ LLVMContextRef LLVMGetTypeContext(LLVMTypeRef Ty) { return wrap(&unwrap(Ty)->getContext()); } -#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) -LLVM_DUMP_METHOD void LLVMDumpType(LLVMTypeRef Ty) { - return unwrap(Ty)->dump(); +void LLVMDumpType(LLVMTypeRef Ty) { + return unwrap(Ty)->print(errs(), /*IsForDebug=*/true); } -#endif char *LLVMPrintTypeToString(LLVMTypeRef Ty) { std::string buf; @@ -658,7 +656,7 @@ void LLVMSetValueName(LLVMValueRef Val, const char *Na unwrap(Val)->setName(Name); } -LLVM_DUMP_METHOD void LLVMDumpValue(LLVMValueRef Val) { +void LLVMDumpValue(LLVMValueRef Val) { unwrap(Val)->print(errs(), /*IsForDebug=*/true); } Modified: vendor/llvm/dist-release_60/lib/MC/MCObjectFileInfo.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/MC/MCObjectFileInfo.cpp Wed Jun 27 19:10:32 2018 (r335719) +++ vendor/llvm/dist-release_60/lib/MC/MCObjectFileInfo.cpp Wed Jun 27 19:14:09 2018 (r335720) @@ -289,6 +289,8 @@ void MCObjectFileInfo::initELFMCObjectFileInfo(const T case Triple::mips64el: FDECFIEncoding = dwarf::DW_EH_PE_sdata8; break; + case Triple::ppc64: + case Triple::ppc64le: case Triple::x86_64: FDECFIEncoding = dwarf::DW_EH_PE_pcrel | (Large ? dwarf::DW_EH_PE_sdata8 : dwarf::DW_EH_PE_sdata4); Modified: vendor/llvm/dist-release_60/lib/Support/CMakeLists.txt ============================================================================== --- vendor/llvm/dist-release_60/lib/Support/CMakeLists.txt Wed Jun 27 19:10:32 2018 (r335719) +++ vendor/llvm/dist-release_60/lib/Support/CMakeLists.txt Wed Jun 27 19:14:09 2018 (r335720) @@ -13,8 +13,13 @@ elseif( CMAKE_HOST_UNIX ) if( HAVE_LIBDL ) set(system_libs ${system_libs} ${CMAKE_DL_LIBS}) endif() - if( HAVE_BACKTRACE ) - set(system_libs ${system_libs} ${Backtrace_LIBRARIES}) + if( HAVE_BACKTRACE AND NOT "${Backtrace_LIBRARIES}" STREQUAL "" ) + # On BSDs, CMake returns a fully qualified path to the backtrace library. + # We need to remove the path and the 'lib' prefix, to make it look like a + # regular short library name, suitable for appending to a -l link flag. + get_filename_component(Backtrace_LIBFILE ${Backtrace_LIBRARIES} NAME_WE) + STRING(REGEX REPLACE "^lib" "" Backtrace_LIBFILE ${Backtrace_LIBFILE}) + set(system_libs ${system_libs} ${Backtrace_LIBFILE}) endif() if(LLVM_ENABLE_TERMINFO) if(HAVE_TERMINFO) Modified: vendor/llvm/dist-release_60/lib/Support/Host.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/Support/Host.cpp Wed Jun 27 19:10:32 2018 (r335719) +++ vendor/llvm/dist-release_60/lib/Support/Host.cpp Wed Jun 27 19:14:09 2018 (r335720) @@ -1009,7 +1009,7 @@ StringRef sys::getHostCPUName() { #include "llvm/Support/X86TargetParser.def" // Now check types. -#define X86_CPU_SUBTYPE(ARCHNAME, ENUM) \ +#define X86_CPU_TYPE(ARCHNAME, ENUM) \ if (Type == X86::ENUM) \ return ARCHNAME; #include "llvm/Support/X86TargetParser.def" Modified: vendor/llvm/dist-release_60/lib/Target/AArch64/AArch64AsmPrinter.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/Target/AArch64/AArch64AsmPrinter.cpp Wed Jun 27 19:10:32 2018 (r335719) +++ vendor/llvm/dist-release_60/lib/Target/AArch64/AArch64AsmPrinter.cpp Wed Jun 27 19:14:09 2018 (r335720) @@ -299,6 +299,11 @@ void AArch64AsmPrinter::printOperand(const MachineInst printOffset(MO.getOffset(), O); break; } + case MachineOperand::MO_BlockAddress: { + MCSymbol *Sym = GetBlockAddressSymbol(MO.getBlockAddress()); + Sym->print(O, MAI); + break; + } } } Modified: vendor/llvm/dist-release_60/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp Wed Jun 27 19:10:32 2018 (r335719) +++ vendor/llvm/dist-release_60/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp Wed Jun 27 19:14:09 2018 (r335720) @@ -46,6 +46,7 @@ #include "llvm/Pass.h" #include "llvm/Support/Casting.h" #include "llvm/Support/Debug.h" +#include "llvm/Support/DebugCounter.h" #include "llvm/Support/raw_ostream.h" #include <cassert> #include <iterator> @@ -60,6 +61,8 @@ STATISTIC(NumCollisionsAvoided, "Number of HW prefetch tag collisions avoided"); STATISTIC(NumCollisionsNotAvoided, "Number of HW prefetch tag collisions not avoided due to lack of regsiters"); +DEBUG_COUNTER(FixCounter, "falkor-hwpf", + "Controls which tag collisions are avoided"); namespace { @@ -728,6 +731,21 @@ void FalkorHWPFFix::runOnLoop(MachineLoop &L, MachineF bool Fixed = false; DEBUG(dbgs() << "Attempting to fix tag collision: " << MI); + + if (!DebugCounter::shouldExecute(FixCounter)) { + DEBUG(dbgs() << "Skipping fix due to debug counter:\n " << MI); + continue; + } + + // Add the non-base registers of MI as live so we don't use them as + // scratch registers. + for (unsigned OpI = 0, OpE = MI.getNumOperands(); OpI < OpE; ++OpI) { + if (OpI == static_cast<unsigned>(LdI.BaseRegIdx)) + continue; + MachineOperand &MO = MI.getOperand(OpI); + if (MO.isReg() && MO.readsReg()) + LR.addReg(MO.getReg()); + } for (unsigned ScratchReg : AArch64::GPR64RegClass) { if (!LR.available(ScratchReg) || MRI.isReserved(ScratchReg)) Modified: vendor/llvm/dist-release_60/lib/Target/AArch64/AArch64FrameLowering.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/Target/AArch64/AArch64FrameLowering.cpp Wed Jun 27 19:10:32 2018 (r335719) +++ vendor/llvm/dist-release_60/lib/Target/AArch64/AArch64FrameLowering.cpp Wed Jun 27 19:14:09 2018 (r335720) @@ -917,6 +917,8 @@ int AArch64FrameLowering::resolveFrameIndexReference(c int FPOffset = MFI.getObjectOffset(FI) + FixedObject + 16; int Offset = MFI.getObjectOffset(FI) + MFI.getStackSize(); bool isFixed = MFI.isFixedObjectIndex(FI); + bool isCSR = !isFixed && MFI.getObjectOffset(FI) >= + -((int)AFI->getCalleeSavedStackSize()); // Use frame pointer to reference fixed objects. Use it for locals if // there are VLAs or a dynamically realigned SP (and thus the SP isn't @@ -930,6 +932,12 @@ int AArch64FrameLowering::resolveFrameIndexReference(c // Argument access should always use the FP. if (isFixed) { UseFP = hasFP(MF); + } else if (isCSR && RegInfo->needsStackRealignment(MF)) { + // References to the CSR area must use FP if we're re-aligning the stack + // since the dynamically-sized alignment padding is between the SP/BP and + // the CSR area. + assert(hasFP(MF) && "Re-aligned stack must have frame pointer"); + UseFP = true; } else if (hasFP(MF) && !RegInfo->hasBasePointer(MF) && !RegInfo->needsStackRealignment(MF)) { // Use SP or FP, whichever gives us the best chance of the offset @@ -947,9 +955,9 @@ int AArch64FrameLowering::resolveFrameIndexReference(c } } - assert((isFixed || !RegInfo->needsStackRealignment(MF) || !UseFP) && + assert(((isFixed || isCSR) || !RegInfo->needsStackRealignment(MF) || !UseFP) && "In the presence of dynamic stack pointer realignment, " - "non-argument objects cannot be accessed through the frame pointer"); + "non-argument/CSR objects cannot be accessed through the frame pointer"); if (UseFP) { FrameReg = RegInfo->getFrameRegister(MF); Modified: vendor/llvm/dist-release_60/lib/Target/AArch64/AArch64ISelLowering.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/Target/AArch64/AArch64ISelLowering.cpp Wed Jun 27 19:10:32 2018 (r335719) +++ vendor/llvm/dist-release_60/lib/Target/AArch64/AArch64ISelLowering.cpp Wed Jun 27 19:14:09 2018 (r335720) @@ -4930,7 +4930,8 @@ bool AArch64TargetLowering::isOffsetFoldingLegal( bool AArch64TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { // We can materialize #0.0 as fmov $Rd, XZR for 64-bit and 32-bit cases. // FIXME: We should be able to handle f128 as well with a clever lowering. - if (Imm.isPosZero() && (VT == MVT::f16 || VT == MVT::f64 || VT == MVT::f32)) { + if (Imm.isPosZero() && (VT == MVT::f64 || VT == MVT::f32 || + (VT == MVT::f16 && Subtarget->hasFullFP16()))) { DEBUG(dbgs() << "Legal fp imm: materialize 0 using the zero register\n"); return true; } @@ -5066,7 +5067,7 @@ SDValue AArch64TargetLowering::getRecipEstimate(SDValu // Table of Constraints // TODO: This is the current set of constraints supported by ARM for the -// compiler, not all of them may make sense, e.g. S may be difficult to support. +// compiler, not all of them may make sense. // // r - A general register // w - An FP/SIMD register of some size in the range v0-v31 @@ -5126,6 +5127,8 @@ AArch64TargetLowering::getConstraintType(StringRef Con // currently handle addresses it is the same as 'r'. case 'Q': return C_Memory; + case 'S': // A symbolic address + return C_Other; } } return TargetLowering::getConstraintType(Constraint); @@ -5250,6 +5253,23 @@ void AArch64TargetLowering::LowerAsmOperandForConstrai Result = DAG.getRegister(AArch64::WZR, MVT::i32); break; } + case 'S': { + // An absolute symbolic address or label reference. + if (const GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op)) { + Result = DAG.getTargetGlobalAddress(GA->getGlobal(), SDLoc(Op), + GA->getValueType(0)); + } else if (const BlockAddressSDNode *BA = + dyn_cast<BlockAddressSDNode>(Op)) { + Result = + DAG.getTargetBlockAddress(BA->getBlockAddress(), BA->getValueType(0)); + } else if (const ExternalSymbolSDNode *ES = + dyn_cast<ExternalSymbolSDNode>(Op)) { + Result = + DAG.getTargetExternalSymbol(ES->getSymbol(), ES->getValueType(0)); + } else + return; + break; + } case 'I': case 'J': @@ -9637,6 +9657,15 @@ static SDValue performPostLD1Combine(SDNode *N, if (LD->getOpcode() != ISD::LOAD) return SDValue(); + // The vector lane must be a constant in the LD1LANE opcode. + SDValue Lane; + if (IsLaneOp) { + Lane = N->getOperand(2); + auto *LaneC = dyn_cast<ConstantSDNode>(Lane); + if (!LaneC || LaneC->getZExtValue() >= VT.getVectorNumElements()) + return SDValue(); + } + LoadSDNode *LoadSDN = cast<LoadSDNode>(LD); EVT MemVT = LoadSDN->getMemoryVT(); // Check if memory operand is the same type as the vector element. @@ -9693,7 +9722,7 @@ static SDValue performPostLD1Combine(SDNode *N, Ops.push_back(LD->getOperand(0)); // Chain if (IsLaneOp) { Ops.push_back(Vector); // The vector to be inserted - Ops.push_back(N->getOperand(2)); // The lane to be inserted in the vector + Ops.push_back(Lane); // The lane to be inserted in the vector } Ops.push_back(Addr); Ops.push_back(Inc); Modified: vendor/llvm/dist-release_60/lib/Target/AArch64/AArch64InstrInfo.td ============================================================================== --- vendor/llvm/dist-release_60/lib/Target/AArch64/AArch64InstrInfo.td Wed Jun 27 19:10:32 2018 (r335719) +++ vendor/llvm/dist-release_60/lib/Target/AArch64/AArch64InstrInfo.td Wed Jun 27 19:14:09 2018 (r335720) @@ -2713,7 +2713,7 @@ defm FMOV : UnscaledConversion<"fmov">; // Add pseudo ops for FMOV 0 so we can mark them as isReMaterializable let isReMaterializable = 1, isCodeGenOnly = 1, isAsCheapAsAMove = 1 in { def FMOVH0 : Pseudo<(outs FPR16:$Rd), (ins), [(set f16:$Rd, (fpimm0))]>, - Sched<[WriteF]>; + Sched<[WriteF]>, Requires<[HasFullFP16]>; def FMOVS0 : Pseudo<(outs FPR32:$Rd), (ins), [(set f32:$Rd, (fpimm0))]>, Sched<[WriteF]>; def FMOVD0 : Pseudo<(outs FPR64:$Rd), (ins), [(set f64:$Rd, (fpimm0))]>, Modified: vendor/llvm/dist-release_60/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp Wed Jun 27 19:10:32 2018 (r335719) +++ vendor/llvm/dist-release_60/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp Wed Jun 27 19:14:09 2018 (r335720) @@ -147,6 +147,7 @@ extern "C" void LLVMInitializeAMDGPUTarget() { initializeR600PacketizerPass(*PR); initializeR600ExpandSpecialInstrsPassPass(*PR); initializeR600VectorRegMergerPass(*PR); + initializeGlobalISel(*PR); initializeAMDGPUDAGToDAGISelPass(*PR); initializeSILowerI1CopiesPass(*PR); initializeSIFixSGPRCopiesPass(*PR); Modified: vendor/llvm/dist-release_60/lib/Target/AMDGPU/SIISelLowering.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/Target/AMDGPU/SIISelLowering.cpp Wed Jun 27 19:10:32 2018 (r335719) +++ vendor/llvm/dist-release_60/lib/Target/AMDGPU/SIISelLowering.cpp Wed Jun 27 19:14:09 2018 (r335720) @@ -358,6 +358,7 @@ SITargetLowering::SITargetLowering(const TargetMachine setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16, Promote); setOperationAction(ISD::CTLZ, MVT::i16, Promote); setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16, Promote); + setOperationAction(ISD::CTPOP, MVT::i16, Promote); setOperationAction(ISD::SELECT_CC, MVT::i16, Expand); Modified: vendor/llvm/dist-release_60/lib/Target/AMDGPU/SIInstructions.td ============================================================================== --- vendor/llvm/dist-release_60/lib/Target/AMDGPU/SIInstructions.td Wed Jun 27 19:10:32 2018 (r335719) +++ vendor/llvm/dist-release_60/lib/Target/AMDGPU/SIInstructions.td Wed Jun 27 19:14:09 2018 (r335720) @@ -726,6 +726,10 @@ def : GCNPat < (i32 (add (i32 (ctpop i32:$popcnt)), i32:$val)), (V_BCNT_U32_B32_e64 $popcnt, $val) >; +def : GCNPat < + (i16 (add (i16 (trunc (ctpop i32:$popcnt))), i16:$val)), + (V_BCNT_U32_B32_e64 $popcnt, $val) +>; /********** ============================================ **********/ /********** Extraction, Insertion, Building and Casting **********/ Modified: vendor/llvm/dist-release_60/lib/Target/ARM/ARMBaseInstrInfo.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/Target/ARM/ARMBaseInstrInfo.cpp Wed Jun 27 19:10:32 2018 (r335719) +++ vendor/llvm/dist-release_60/lib/Target/ARM/ARMBaseInstrInfo.cpp Wed Jun 27 19:14:09 2018 (r335720) @@ -4864,12 +4864,14 @@ bool ARMBaseInstrInfo::getRegSequenceLikeInputs( // Populate the InputRegs accordingly. // rY const MachineOperand *MOReg = &MI.getOperand(1); - InputRegs.push_back( - RegSubRegPairAndIdx(MOReg->getReg(), MOReg->getSubReg(), ARM::ssub_0)); + if (!MOReg->isUndef()) + InputRegs.push_back(RegSubRegPairAndIdx(MOReg->getReg(), + MOReg->getSubReg(), ARM::ssub_0)); // rZ MOReg = &MI.getOperand(2); - InputRegs.push_back( - RegSubRegPairAndIdx(MOReg->getReg(), MOReg->getSubReg(), ARM::ssub_1)); + if (!MOReg->isUndef()) + InputRegs.push_back(RegSubRegPairAndIdx(MOReg->getReg(), + MOReg->getSubReg(), ARM::ssub_1)); return true; } llvm_unreachable("Target dependent opcode missing"); @@ -4888,6 +4890,8 @@ bool ARMBaseInstrInfo::getExtractSubregLikeInputs( // rX = EXTRACT_SUBREG dZ, ssub_0 // rY = EXTRACT_SUBREG dZ, ssub_1 const MachineOperand &MOReg = MI.getOperand(2); + if (MOReg.isUndef()) + return false; InputReg.Reg = MOReg.getReg(); InputReg.SubReg = MOReg.getSubReg(); InputReg.SubIdx = DefIdx == 0 ? ARM::ssub_0 : ARM::ssub_1; @@ -4907,6 +4911,8 @@ bool ARMBaseInstrInfo::getInsertSubregLikeInputs( // dX = VSETLNi32 dY, rZ, imm const MachineOperand &MOBaseReg = MI.getOperand(1); const MachineOperand &MOInsertedReg = MI.getOperand(2); + if (MOInsertedReg.isUndef()) + return false; const MachineOperand &MOIndex = MI.getOperand(3); BaseReg.Reg = MOBaseReg.getReg(); BaseReg.SubReg = MOBaseReg.getSubReg(); Modified: vendor/llvm/dist-release_60/lib/Target/ARM/ARMComputeBlockSize.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/Target/ARM/ARMComputeBlockSize.cpp Wed Jun 27 19:10:32 2018 (r335719) +++ vendor/llvm/dist-release_60/lib/Target/ARM/ARMComputeBlockSize.cpp Wed Jun 27 19:14:09 2018 (r335720) @@ -35,6 +35,7 @@ mayOptimizeThumb2Instruction(const MachineInstr *MI) { case ARM::tBcc: // optimizeThumb2JumpTables. case ARM::t2BR_JT: + case ARM::tBR_JTr: return true; } return false; Modified: vendor/llvm/dist-release_60/lib/Target/Mips/AsmParser/MipsAsmParser.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/Target/Mips/AsmParser/MipsAsmParser.cpp Wed Jun 27 19:10:32 2018 (r335719) +++ vendor/llvm/dist-release_60/lib/Target/Mips/AsmParser/MipsAsmParser.cpp Wed Jun 27 19:14:09 2018 (r335720) @@ -5136,6 +5136,7 @@ unsigned MipsAsmParser::checkTargetMatchPredicate(MCIn // It also applies for registers Rt and Rs of microMIPSr6 jalrc.hb instruction // and registers Rd and Base for microMIPS lwp instruction case Mips::JALR_HB: + case Mips::JALR_HB64: case Mips::JALRC_HB_MMR6: case Mips::JALRC_MMR6: if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) Modified: vendor/llvm/dist-release_60/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp ============================================================================== --- vendor/llvm/dist-release_60/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp Wed Jun 27 19:10:32 2018 (r335719) +++ vendor/llvm/dist-release_60/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp Wed Jun 27 19:14:09 2018 (r335720) @@ -225,6 +225,8 @@ unsigned MipsELFObjectWriter::getRelocType(MCContext & switch (Kind) { case Mips::fixup_Mips_NONE: return ELF::R_MIPS_NONE; + case FK_Data_1: + report_fatal_error("MIPS does not support one byte relocations"); case Mips::fixup_Mips_16: case FK_Data_2: return IsPCRel ? ELF::R_MIPS_PC16 : ELF::R_MIPS_16; Modified: vendor/llvm/dist-release_60/lib/Target/Mips/MicroMips32r6InstrInfo.td ============================================================================== --- vendor/llvm/dist-release_60/lib/Target/Mips/MicroMips32r6InstrInfo.td Wed Jun 27 19:10:32 2018 (r335719) +++ vendor/llvm/dist-release_60/lib/Target/Mips/MicroMips32r6InstrInfo.td Wed Jun 27 19:14:09 2018 (r335720) @@ -1886,6 +1886,12 @@ let AddedComplexity = 41 in { def TAILCALL_MMR6 : TailCall<BC_MMR6, brtarget26_mm>, ISA_MICROMIPS32R6; +def TAILCALLREG_MMR6 : TailCallReg<JRC16_MM, GPR32Opnd>, ISA_MICROMIPS32R6; + +def PseudoIndirectBranch_MMR6 : PseudoIndirectBranchBase<JRC16_MMR6, + GPR32Opnd>, + ISA_MICROMIPS32R6; + def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)), (TAILCALL_MMR6 tglobaladdr:$dst)>, ISA_MICROMIPS32R6; Modified: vendor/llvm/dist-release_60/lib/Target/Mips/MicroMipsInstrInfo.td ============================================================================== --- vendor/llvm/dist-release_60/lib/Target/Mips/MicroMipsInstrInfo.td Wed Jun 27 19:10:32 2018 (r335719) +++ vendor/llvm/dist-release_60/lib/Target/Mips/MicroMipsInstrInfo.td Wed Jun 27 19:14:09 2018 (r335720) @@ -1003,6 +1003,12 @@ let DecoderNamespace = "MicroMips", Predicates = [InMi def TAILCALL_MM : TailCall<J_MM, jmptarget_mm>, ISA_MIPS1_NOT_32R6_64R6; +def TAILCALLREG_MM : TailCallReg<JRC16_MM, GPR32Opnd>, + ISA_MICROMIPS32_NOT_MIPS32R6; + +def PseudoIndirectBranch_MM : PseudoIndirectBranchBase<JR_MM, GPR32Opnd>, + ISA_MICROMIPS32_NOT_MIPS32R6; + let DecoderNamespace = "MicroMips" in { def RDHWR_MM : MMRel, R6MMR6Rel, ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM_MM, ISA_MICROMIPS32_NOT_MIPS32R6; Modified: vendor/llvm/dist-release_60/lib/Target/Mips/Mips.td ============================================================================== --- vendor/llvm/dist-release_60/lib/Target/Mips/Mips.td Wed Jun 27 19:10:32 2018 (r335719) +++ vendor/llvm/dist-release_60/lib/Target/Mips/Mips.td Wed Jun 27 19:14:09 2018 (r335720) @@ -193,6 +193,10 @@ def FeatureMT : SubtargetFeature<"mt", "HasMT", "true" def FeatureLongCalls : SubtargetFeature<"long-calls", "UseLongCalls", "true", "Disable use of the jal instruction">; +def FeatureUseIndirectJumpsHazard : SubtargetFeature<"use-indirect-jump-hazard", + "UseIndirectJumpsHazard", + "true", "Use indirect jump" + " guards to prevent certain speculation based attacks">; //===----------------------------------------------------------------------===// // Mips processors supported. //===----------------------------------------------------------------------===// Modified: vendor/llvm/dist-release_60/lib/Target/Mips/Mips32r6InstrInfo.td ============================================================================== --- vendor/llvm/dist-release_60/lib/Target/Mips/Mips32r6InstrInfo.td Wed Jun 27 19:10:32 2018 (r335719) +++ vendor/llvm/dist-release_60/lib/Target/Mips/Mips32r6InstrInfo.td Wed Jun 27 19:14:09 2018 (r335720) @@ -1036,3 +1036,42 @@ def : MipsPat<(select i32:$cond, immz, i32:$f), (SELEQZ i32:$f, i32:$cond)>, ISA_MIPS32R6; } + +// Pseudo instructions +let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, hasDelaySlot = 1, + hasExtraSrcRegAllocReq = 1, isCTI = 1, Defs = [AT] in { + class TailCallRegR6<Instruction JumpInst, Register RT, RegisterOperand RO> : + PseudoSE<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)], II_JR>, + PseudoInstExpansion<(JumpInst RT:$rt, RO:$rs)>; +} + +class PseudoIndirectBranchBaseR6<Instruction JumpInst, Register RT, + RegisterOperand RO> : + MipsPseudo<(outs), (ins RO:$rs), [(brind RO:$rs)], + II_IndirectBranchPseudo>, + PseudoInstExpansion<(JumpInst RT:$rt, RO:$rs)> { + let isTerminator=1; + let isBarrier=1; + let hasDelaySlot = 1; + let isBranch = 1; + let isIndirectBranch = 1; + bit isCTI = 1; +} + + +let AdditionalPredicates = [NotInMips16Mode, NotInMicroMips, + NoIndirectJumpGuards] in { + def TAILCALLR6REG : TailCallRegR6<JALR, ZERO, GPR32Opnd>, ISA_MIPS32R6; + def PseudoIndirectBranchR6 : PseudoIndirectBranchBaseR6<JALR, ZERO, + GPR32Opnd>, + ISA_MIPS32R6; +} + +let AdditionalPredicates = [NotInMips16Mode, NotInMicroMips, + UseIndirectJumpsHazard] in { + def TAILCALLHBR6REG : TailCallReg<JR_HB_R6, GPR32Opnd>, ISA_MIPS32R6; + def PseudoIndrectHazardBranchR6 : PseudoIndirectBranchBase<JR_HB_R6, + GPR32Opnd>, + ISA_MIPS32R6; +} + Modified: vendor/llvm/dist-release_60/lib/Target/Mips/Mips64InstrInfo.td ============================================================================== --- vendor/llvm/dist-release_60/lib/Target/Mips/Mips64InstrInfo.td Wed Jun 27 19:10:32 2018 (r335719) +++ vendor/llvm/dist-release_60/lib/Target/Mips/Mips64InstrInfo.td Wed Jun 27 19:14:09 2018 (r335720) @@ -240,13 +240,32 @@ let isCodeGenOnly = 1 in { def BGTZ64 : CBranchZero<"bgtz", brtarget, setgt, GPR64Opnd>, BGEZ_FM<7, 0>; def BLEZ64 : CBranchZero<"blez", brtarget, setle, GPR64Opnd>, BGEZ_FM<6, 0>; def BLTZ64 : CBranchZero<"bltz", brtarget, setlt, GPR64Opnd>, BGEZ_FM<1, 0>; - def JALR64Pseudo : JumpLinkRegPseudo<GPR64Opnd, JALR, RA, GPR32Opnd>; + let AdditionalPredicates = [NoIndirectJumpGuards] in + def JALR64Pseudo : JumpLinkRegPseudo<GPR64Opnd, JALR, RA, GPR32Opnd>; } +let AdditionalPredicates = [NotInMicroMips], + DecoderNamespace = "Mips64" in { + def JR_HB64 : JR_HB_DESC<GPR64Opnd>, JR_HB_ENC, ISA_MIPS32_NOT_32R6_64R6; + def JALR_HB64 : JALR_HB_DESC<GPR64Opnd>, JALR_HB_ENC, ISA_MIPS32R2; +} +def PseudoReturn64 : PseudoReturnBase<GPR64Opnd>; -def TAILCALLREG64 : TailCallReg<GPR64Opnd>; +let AdditionalPredicates = [NotInMips16Mode, NotInMicroMips, + NoIndirectJumpGuards] in { + def TAILCALLREG64 : TailCallReg<JR64, GPR64Opnd>, ISA_MIPS3_NOT_32R6_64R6, + PTR_64; + def PseudoIndirectBranch64 : PseudoIndirectBranchBase<JR64, GPR64Opnd>, + ISA_MIPS3_NOT_32R6_64R6; +} -def PseudoReturn64 : PseudoReturnBase<GPR64Opnd>; -def PseudoIndirectBranch64 : PseudoIndirectBranchBase<GPR64Opnd>; +let AdditionalPredicates = [NotInMips16Mode, NotInMicroMips, + UseIndirectJumpsHazard] in { + def TAILCALLREGHB64 : TailCallReg<JR_HB64, GPR64Opnd>, + ISA_MIPS32R2_NOT_32R6_64R6, PTR_64; + def PseudoIndirectHazardBranch64 : PseudoIndirectBranchBase<JR_HB64, + GPR64Opnd>, + ISA_MIPS32R2_NOT_32R6_64R6; +} /// Multiply and Divide Instructions. let AdditionalPredicates = [NotInMicroMips] in { @@ -536,6 +555,10 @@ def DMTC2 : MTC3OP<"dmtc2", COP2Opnd, GPR64Opnd, II_DM ISA_MIPS3; } + +let AdditionalPredicates = [UseIndirectJumpsHazard] in + def JALRHB64Pseudo : JumpLinkRegPseudo<GPR64Opnd, JALR_HB64, RA_64>; + //===----------------------------------------------------------------------===// // Arbitrary patterns that map to one or more instructions //===----------------------------------------------------------------------===// @@ -843,7 +866,8 @@ let AdditionalPredicates = [NotInMicroMips] in { def : MipsInstAlias<"dext $rt, $rs, $pos, $size", (DEXTU GPR64Opnd:$rt, GPR64Opnd:$rs, uimm5_plus32:$pos, uimm5_plus1:$size), 0>, ISA_MIPS64R2; - + def : MipsInstAlias<"jalr.hb $rs", (JALR_HB64 RA_64, GPR64Opnd:$rs), 1>, + ISA_MIPS64; // Two operand (implicit 0 selector) versions: def : MipsInstAlias<"dmtc0 $rt, $rd", (DMTC0 COP0Opnd:$rd, GPR64Opnd:$rt, 0), 0>; Modified: vendor/llvm/dist-release_60/lib/Target/Mips/Mips64r6InstrInfo.td ============================================================================== --- vendor/llvm/dist-release_60/lib/Target/Mips/Mips64r6InstrInfo.td Wed Jun 27 19:10:32 2018 (r335719) +++ vendor/llvm/dist-release_60/lib/Target/Mips/Mips64r6InstrInfo.td Wed Jun 27 19:14:09 2018 (r335720) @@ -104,6 +104,16 @@ class JIC64_DESC : JMP_IDX_COMPACT_DESC_BASE<"jic", jm class LL64_R6_DESC : LL_R6_DESC_BASE<"ll", GPR32Opnd, mem_simm9, II_LL>; class SC64_R6_DESC : SC_R6_DESC_BASE<"sc", GPR32Opnd, II_SC>; + +class JR_HB64_R6_DESC : JR_HB_DESC_BASE<"jr.hb", GPR64Opnd> { + bit isBranch = 1; *** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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