From owner-svn-src-all@FreeBSD.ORG Sat Mar 21 05:59:47 2015 Return-Path: Delivered-To: svn-src-all@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [8.8.178.115]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id 31616D6; Sat, 21 Mar 2015 05:59:47 +0000 (UTC) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 1CB52948; Sat, 21 Mar 2015 05:59:47 +0000 (UTC) Received: from svn.freebsd.org ([127.0.1.70]) by svn.freebsd.org (8.14.9/8.14.9) with ESMTP id t2L5xkR2004957; Sat, 21 Mar 2015 05:59:46 GMT (envelope-from adrian@FreeBSD.org) Received: (from adrian@localhost) by svn.freebsd.org (8.14.9/8.14.9/Submit) id t2L5xkc8004956; Sat, 21 Mar 2015 05:59:46 GMT (envelope-from adrian@FreeBSD.org) Message-Id: <201503210559.t2L5xkc8004956@svn.freebsd.org> X-Authentication-Warning: svn.freebsd.org: adrian set sender to adrian@FreeBSD.org using -f From: Adrian Chadd Date: Sat, 21 Mar 2015 05:59:46 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r280313 - head/sys/mips/atheros X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 21 Mar 2015 05:59:47 -0000 Author: adrian Date: Sat Mar 21 05:59:45 2015 New Revision: 280313 URL: https://svnweb.freebsd.org/changeset/base/280313 Log: Note that the AR724x PCIe registers are actually from the PCI_CTRL register range. Modified: head/sys/mips/atheros/ar724xreg.h Modified: head/sys/mips/atheros/ar724xreg.h ============================================================================== --- head/sys/mips/atheros/ar724xreg.h Sat Mar 21 04:39:33 2015 (r280312) +++ head/sys/mips/atheros/ar724xreg.h Sat Mar 21 05:59:45 2015 (r280313) @@ -78,7 +78,7 @@ #define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000F0000) #define AR724X_PCI_CTRL_SIZE 0x100 -/* PCI config registers */ +/* PCI config registers - AR724X_PCI_CTRL_BASE */ #define AR724X_PCI_APP 0x180f0000 #define AR724X_PCI_APP_LTSSM_ENABLE (1 << 0) #define AR724X_PCI_RESET 0x180f0018