Date: Sun, 6 May 2007 22:39:31 GMT From: Bruce M Simpson <bms@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 119378 for review Message-ID: <200705062239.l46MdVNR026838@repoman.freebsd.org>
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http://perforce.freebsd.org/chv.cgi?CH=119378 Change 119378 by bms@bms_anglepoise on 2007/05/06 22:38:49 add macros for broadcom custom MIPS register access. pll probing doesn't work; we need device siba to exist first. hardcode sentry5 clock @200Mhz for now. Affected files ... .. //depot/projects/mips2/src/sys/mips/conf/SENTRY5#2 edit .. //depot/projects/mips2/src/sys/mips/mips/tick.c#14 edit .. //depot/projects/mips2/src/sys/mips/mips32/sentry5/sentry5reg.h#2 edit Differences ... ==== //depot/projects/mips2/src/sys/mips/conf/SENTRY5#2 (text+ko) ==== @@ -1,6 +1,6 @@ # # $FreeBSD$ -# $P4: //depot/projects/mips2/src/sys/mips/conf/SENTRY5#1 $ +# $P4: //depot/projects/mips2/src/sys/mips/conf/SENTRY5#2 $ # # The Broadcom Sentry5 series of processors and boards is very commonly # used in COTS hardware including the Netgear WGT634U. @@ -57,12 +57,14 @@ options INVARIANTS options INVARIANT_SUPPORT -#device sbmips # TODO: SiliconBackplane board support +# TODO: SiliconBackplane board support +#device siba device pci device uart device uart_ns8250 +# XXX Should this be bce or bfe? device bfe device miibus ==== //depot/projects/mips2/src/sys/mips/mips/tick.c#14 (text+ko) ==== @@ -59,6 +59,11 @@ #include <isa/rtc.h> #endif +#ifdef CPU_SENTRY5 +#include <machine/cpuregs.h> +#include <mips/mips32/sentry5/sentry5reg.h> +#endif + /* * Default is to assume a CPU pipeline clock of 100Mhz, and * that CP0_COUNT increments every 2 cycles. @@ -118,7 +123,6 @@ return ((uint64_t)mips_rd_count()); } -/* XXX TODO: Calibrate SENTRY5 clock from custom CP0 PLL* registers. */ void tick_init_params(void) { @@ -162,6 +166,39 @@ counterval[1] = mips_rd_count(); counter_freq = counterval[1] - counterval[0]; +#elif defined(CPU_SENTRY5) +# if 0 + /* + * Probe the Broadcom Sentry5's on-chip PLL clock registers + * and discover the CPU pipeline clock and bus clock + * multipliers from this. + * XXX: Wrong place. You have to ask the ChipCommon + * or External Interface cores on the SiBa. + */ + uint32_t busmult, cpumult, refclock, clkcfg1; +#define S5_CLKCFG1_REFCLOCK_MASK 0x0000001F +#define S5_CLKCFG1_BUSMULT_MASK 0x000003E0 +#define S5_CLKCFG1_BUSMULT_SHIFT 5 +#define S5_CLKCFG1_CPUMULT_MASK 0xFFFFFC00 +#define S5_CLKCFG1_CPUMULT_SHIFT 10 + + counter_freq = 100000000; /* XXX */ + + clkcfg1 = s5_rd_clkcfg1(); + printf("clkcfg1 = 0x%08x\n", clkcfg1); + + refclock = clkcfg1 & 0x1F; + busmult = ((clkcfg1 & 0x000003E0) >> 5) + 1; + cpumult = ((clkcfg1 & 0xFFFFFC00) >> 10) + 1; + + printf("refclock = %u\n", refclock); + printf("busmult = %u\n", busmult); + printf("cpumult = %u\n", cpumult); + + counter_freq = cpumult * refclock; +# else + counter_freq = 200 * 1000 * 1000; /* Sentry5 is 200MHz */ +# endif #else /* * Use a completely fictional hardcoded default. ==== //depot/projects/mips2/src/sys/mips/mips32/sentry5/sentry5reg.h#2 (text+ko) ==== @@ -10,4 +10,49 @@ #define SENTRY5_EXTIFADR 0x1F000000 #define SENTRY5_DORESET 0x80 +/* + * Custom CP0 register macros. + * XXX: This really needs the mips cpuregs.h file for the barrier. + */ +#define S5_RDRW32_C0P0_CUST22(n,r) \ +static __inline u_int32_t \ +s5_rd_ ## n (void) \ +{ \ + int v0; \ + __asm __volatile ("mfc0 %[v0], $22, "__XSTRING(r)" ;" \ + : [v0] "=&r"(v0)); \ + /*mips_barrier();*/ \ + return (v0); \ +} \ +static __inline void \ +s5_wr_ ## n (u_int32_t a0) \ +{ \ + __asm __volatile ("mtc0 %[a0], $22, "__XSTRING(r)" ;" \ + __XSTRING(COP0_SYNC)";" \ + "nop;" \ + "nop;" \ + : \ + : [a0] "r"(a0)); \ + /*mips_barrier();*/ \ +} struct __hack + +/* + * All 5 of these sub-registers are used by Linux. + * There is a further custom register at 25 which is not used. + */ +#define S5_CP0_DIAG 0 +#define S5_CP0_CLKCFG1 1 +#define S5_CP0_CLKCFG2 2 +#define S5_CP0_SYNC 3 +#define S5_CP0_CLKCFG3 4 +#define S5_CP0_RESET 5 + +/* s5_[rd|wr]_xxx() */ +S5_RDRW32_C0P0_CUST22(diag, S5_CP0_DIAG); +S5_RDRW32_C0P0_CUST22(clkcfg1, S5_CP0_CLKCFG1); +S5_RDRW32_C0P0_CUST22(clkcfg2, S5_CP0_CLKCFG2); +S5_RDRW32_C0P0_CUST22(sync, S5_CP0_SYNC); +S5_RDRW32_C0P0_CUST22(clkcfg3, S5_CP0_CLKCFG3); +S5_RDRW32_C0P0_CUST22(reset, S5_CP0_RESET); + #endif /* _MIPS32_SENTRY5_SENTRY5REG_H_ */
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