From owner-freebsd-ia64@FreeBSD.ORG Wed Feb 12 19:43:55 2014 Return-Path: Delivered-To: ia64@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [8.8.178.115]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id 7611C7D3; Wed, 12 Feb 2014 19:43:55 +0000 (UTC) Received: from bigwig.baldwin.cx (bigwig.baldwin.cx [IPv6:2001:470:1f11:75::1]) (using TLSv1 with cipher ADH-CAMELLIA256-SHA (256/256 bits)) (No client certificate requested) by mx1.freebsd.org (Postfix) with ESMTPS id 4A7481697; Wed, 12 Feb 2014 19:43:55 +0000 (UTC) Received: from jhbbsd.localnet (unknown [209.249.190.124]) by bigwig.baldwin.cx (Postfix) with ESMTPSA id 5A328B9A9; Wed, 12 Feb 2014 14:43:54 -0500 (EST) From: John Baldwin To: ia64@freebsd.org Subject: Re: svn commit: r261790 - in head/sys: amd64/include dev/acpica dev/cardbus dev/pccbb dev/pci i386/include sparc64/pci x86/include x86/pci x86/x86 Date: Wed, 12 Feb 2014 14:25:48 -0500 User-Agent: KMail/1.13.5 (FreeBSD/8.4-CBSD-20130906; KDE/4.5.5; amd64; ; ) References: <201402120430.s1C4Uctm088069@svn.freebsd.org> In-Reply-To: <201402120430.s1C4Uctm088069@svn.freebsd.org> MIME-Version: 1.0 Content-Type: Text/Plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <201402121425.48635.jhb@freebsd.org> X-Greylist: Sender succeeded SMTP AUTH, not delayed by milter-greylist-4.2.7 (bigwig.baldwin.cx); Wed, 12 Feb 2014 14:43:54 -0500 (EST) Cc: Marcel Moolenaar X-BeenThere: freebsd-ia64@freebsd.org X-Mailman-Version: 2.1.17 Precedence: list List-Id: Porting FreeBSD to the IA-64 List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 12 Feb 2014 19:43:55 -0000 On Tuesday, February 11, 2014 11:30:38 pm John Baldwin wrote: > Author: jhb > Date: Wed Feb 12 04:30:37 2014 > New Revision: 261790 > URL: http://svnweb.freebsd.org/changeset/base/261790 > > Log: > Add support for managing PCI bus numbers. As with BARs and PCI-PCI bridge > I/O windows, the default is to preserve the firmware-assigned resources. > PCI bus numbers are only managed if NEW_PCIB is enabled and the architecture > defines a PCI_RES_BUS resource type. > - Add a helper API to create top-level PCI bus resource managers for each > PCI domain/segment. Host-PCI bridge drivers use this API to allocate > bus numbers from their associated domain. > - Change the PCI bus and CardBus drivers to allocate a bus resource for > their bus number from the parent PCI bridge device. > - Change the PCI-PCI and PCI-CardBus bridge drivers to allocate the > full range of bus numbers from secbus to subbus from their parent bridge. > The drivers also always program their primary bus register. The bridge > drivers also support growing their bus range by extending the bus resource > and updating subbus to match the larger range. > - Add support for managing PCI bus resources to the Host-PCI bridge drivers > used for amd64 and i386 (acpi_pcib, mptable_pcib, legacy_pcib, and qpi_pcib). > - Define a PCI_RES_BUS resource type for amd64 and i386. Since ia64 only uses ACPI Host-PCI bridges, I believe that this can be enabled on ia64 by just adding an appropriate #define for PCI_RES_BUS to . I just have no way to test it. -- John Baldwin