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From: Jung-uk Kim <jkim@FreeBSD.org>
Date: Wed, 6 Apr 2011 23:59:59 +0000 (UTC)
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Subject: cvs commit: src/sys/i386/i386 machdep.c src/sys/i386/include
 atomic.h src/sys/pc98/pc98 machdep.c
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jkim        2011-04-06 23:59:59 UTC

  FreeBSD src repository

  Modified files:
    sys/i386/i386        machdep.c 
    sys/i386/include     atomic.h 
    sys/pc98/pc98        machdep.c 
  Log:
  SVN rev 220404 on 2011-04-06 23:59:59Z by jkim
  
  Implement atomic_load_acq_64(9) and atomic_store_rel_64(9) for i386.  These
  functions are implemented with CMPXCHG8B instruction where it is available,
  i. e., all Pentium-class and later processors.  Note this instruction is
  also used for atomic_store_rel_64() because a simple XCHG-like instruction
  for 64-bit memory access does not exist, unfortunately.  If the processor
  lacks the instruction, i. e., 80486-class CPUs, two 32-bit load/store are
  performed with interrupt temporarily disabled, assuming it does not support
  SMP.  Although this assumption may be little naive, it is true in reality.
  This implementation is inspired by Linux.
  
  Revision  Changes    Path
  1.727     +18 -0     src/sys/i386/i386/machdep.c
  1.57      +86 -0     src/sys/i386/include/atomic.h
  1.444     +17 -0     src/sys/pc98/pc98/machdep.c