From owner-svn-src-all@FreeBSD.ORG Tue Dec 23 04:46:14 2008 Return-Path: Delivered-To: svn-src-all@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 41E2E1065670; Tue, 23 Dec 2008 04:46:14 +0000 (UTC) (envelope-from sam@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id 314BD8FC0C; Tue, 23 Dec 2008 04:46:14 +0000 (UTC) (envelope-from sam@FreeBSD.org) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.3/8.14.3) with ESMTP id mBN4kEtu081097; Tue, 23 Dec 2008 04:46:14 GMT (envelope-from sam@svn.freebsd.org) Received: (from sam@localhost) by svn.freebsd.org (8.14.3/8.14.3/Submit) id mBN4kEkM081096; Tue, 23 Dec 2008 04:46:14 GMT (envelope-from sam@svn.freebsd.org) Message-Id: <200812230446.mBN4kEkM081096@svn.freebsd.org> From: Sam Leffler Date: Tue, 23 Dec 2008 04:46:14 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r186417 - head/sys/arm/include X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 23 Dec 2008 04:46:14 -0000 Author: sam Date: Tue Dec 23 04:46:13 2008 New Revision: 186417 URL: http://svn.freebsd.org/changeset/base/186417 Log: add IXP465 and generic IXP425 definition Modified: head/sys/arm/include/armreg.h Modified: head/sys/arm/include/armreg.h ============================================================================== --- head/sys/arm/include/armreg.h Tue Dec 23 04:44:23 2008 (r186416) +++ head/sys/arm/include/armreg.h Tue Dec 23 04:46:13 2008 (r186417) @@ -171,10 +171,12 @@ #define CPU_ID_80219_400 0x69052e20 /* A0 stepping/revision. */ #define CPU_ID_80219_600 0x69052e30 /* A0 stepping/revision. */ #define CPU_ID_81342 0x69056810 +#define CPU_ID_IXP425 0x690541c0 #define CPU_ID_IXP425_533 0x690541c0 #define CPU_ID_IXP425_400 0x690541d0 #define CPU_ID_IXP425_266 0x690541f0 #define CPU_ID_IXP435 0x69054040 +#define CPU_ID_IXP465 0x69054200 /* ARM3-specific coprocessor 15 registers */ #define ARM3_CP15_FLUSH 1