From owner-freebsd-hardware Mon Oct 14 06:39:27 1996 Return-Path: owner-hardware Received: (from root@localhost) by freefall.freebsd.org (8.7.5/8.7.3) id GAA27664 for hardware-outgoing; Mon, 14 Oct 1996 06:39:27 -0700 (PDT) Received: from hp.com (hp.com [15.255.152.4]) by freefall.freebsd.org (8.7.5/8.7.3) with ESMTP id GAA27644; Mon, 14 Oct 1996 06:39:24 -0700 (PDT) Received: from fakir.india.hp.com by hp.com with ESMTP (1.37.109.16/15.5+ECS 3.3) id AA065350353; Mon, 14 Oct 1996 06:39:17 -0700 Received: from localhost by fakir.india.hp.com with SMTP (1.37.109.16/15.5+ECS 3.3) id AA107472262; Mon, 14 Oct 1996 19:11:02 +0500 Message-Id: <199610141411.AA107472262@fakir.india.hp.com> To: Joe Greco Cc: hackers@freebsd.org, hardware@freebsd.org Subject: Re: AMD 586 runs FreeBSD just FINE In-Reply-To: Your message of "Mon, 14 Oct 1996 08:05:18 EST." <199610141305.IAA23662@brasil.moneng.mei.com> Date: Mon, 14 Oct 1996 19:11:02 +0500 From: A JOSEPH KOSHY Sender: owner-hardware@freebsd.org X-Loop: FreeBSD.org Precedence: bulk >>>> "Joe Greco" writes > That's odd (I think)... I upgraded an ASUS SP3G board from a DX2/66 > to a DX5/133 without a single jumper change... from the SP3G's point > of view it was a _real_ fast DX2/66 :-) I've been running an Am5x86 for some months now on a SiS motherboard. Replacing CPU's isn't generally as simply as dropping in a new CPU over the old one. For example: a) The Am5x86 supports a write-back L1 cache; since most 486's offer a write-thru L1 cache your motherboard needs to understand enough of the AMD bus protocol to allow the chip to work correctly in the presence of other bus masters etc. b) Further, since the chip is overclocked wrt to the system bus, the motherboard needs to feed the correct clock frequencies to the chip. c) Then there is the matter of supply voltages; some of the newer chips run off 3.3 and 3.45 Volts while the older 486's ran off 5V. The motherboard needs to know the right voltage levels to feed the CPU. d) Finally there are pins on some of the newer chips that have defined functionality now which were earlier N/Cs. An example would be the extra pins needed to support cache snooping with a write-back cache in the CPU. The motherboard needs to drive these correctly. Thus some form of jumpering is the norm when changing CPUs. Esp. in case (c) above. Koshy