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Chernikov To: Ryan Libby , "src-committers@freebsd.org" , "svn-src-all@freebsd.org" , "svn-src-head@freebsd.org" In-Reply-To: <202002281832.01SIWaEL071685@repo.freebsd.org> References: <202002281832.01SIWaEL071685@repo.freebsd.org> Subject: Re: svn commit: r358439 - head/sys/amd64/include MIME-Version: 1.0 X-Mailer: Yamail [ http://yandex.ru ] 5.0 Date: Mon, 02 Mar 2020 08:45:27 +0000 Message-Id: <5767791583138727@sas1-c7aad230fe87.qloud-c.yandex.net> Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset=utf-8 X-Rspamd-Queue-Id: 48WDHb2g4hz4GqW X-Spamd-Bar: ------ Authentication-Results: mx1.freebsd.org; dkim=pass header.d=ipfw.ru header.s=mail header.b=pb8F+Yyw; dmarc=none; spf=pass (mx1.freebsd.org: domain of melifaro@ipfw.ru designates 77.88.28.111 as permitted sender) smtp.mailfrom=melifaro@ipfw.ru X-Spamd-Result: default: False [-6.28 / 15.00]; ARC_NA(0.00)[]; TO_DN_EQ_ADDR_SOME(0.00)[]; R_DKIM_ALLOW(-0.20)[ipfw.ru:s=mail]; NEURAL_HAM_MEDIUM(-0.99)[-0.992,0]; FROM_HAS_DN(0.00)[]; RCPT_COUNT_THREE(0.00)[4]; R_SPF_ALLOW(-0.20)[+ip4:77.88.0.0/18]; TO_MATCH_ENVRCPT_ALL(0.00)[]; MIME_GOOD(-0.10)[text/plain]; DMARC_NA(0.00)[ipfw.ru]; NEURAL_HAM_LONG(-1.00)[-1.000,0]; TO_DN_SOME(0.00)[]; RCVD_COUNT_THREE(0.00)[3]; IP_SCORE(-3.69)[ip: (-9.77), ipnet: 77.88.0.0/18(-4.85), asn: 13238(-3.84), country: RU(0.01)]; DKIM_TRACE(0.00)[ipfw.ru:+]; RCVD_IN_DNSWL_LOW(-0.10)[111.28.88.77.list.dnswl.org : 127.0.5.1]; FROM_EQ_ENVFROM(0.00)[]; MIME_TRACE(0.00)[0:+]; ASN(0.00)[asn:13238, ipnet:77.88.0.0/18, country:RU]; RCVD_TLS_LAST(0.00)[] X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 02 Mar 2020 08:45:34 -0000 28.02.2020, 18:32, "Ryan Libby" : > Author: rlibby > Date: Fri Feb 28 18:32:36 2020 > New Revision: 358439 > URL: https://svnweb.freebsd.org/changeset/base/358439 > > Log: >   amd64 atomic.h: minor codegen optimization in flag access > >   Previously the pattern to extract status flags from inline assembly >   blocks was to use setcc in the block to write the flag to a register. >   This was suboptimal in a few ways: >    - It would lead to code like: sete %cl; test %cl; jne, i.e. a flag >      would just be loaded into a register and then reloaded to a flag. >    - The setcc would force the block to use an additional register. >    - If the client code didn't care for the flag value then the setcc >      would be entirely pointless but could not be eliminated by the >      optimizer. > >   A more modern inline asm construct (since gcc 6 and clang 9) allows for This effectively restricts kernel builds by all older compilers. Is there any chance of making it conditional depending on the compiler version/features? >   "flag output operands", where a C variable can be written directly from >   a flag. The optimizer can then use this to produce direct code where >   the flag does not take a trip through a register. > >   In practice this makes each affected operation sequence shorter by five >   bytes of instructions. It's unlikely this has a measurable performance >   impact. > >   Reviewed by: kib, markj, mjg >   Sponsored by: Dell EMC Isilon >   Differential Revision: https://reviews.freebsd.org/D23869 > > Modified: >   head/sys/amd64/include/atomic.h > > Modified: head/sys/amd64/include/atomic.h > ============================================================================== > --- head/sys/amd64/include/atomic.h Fri Feb 28 17:41:46 2020 (r358438) > +++ head/sys/amd64/include/atomic.h Fri Feb 28 18:32:36 2020 (r358439) > @@ -201,9 +201,8 @@ atomic_cmpset_##TYPE(volatile u_##TYPE *dst, u_##TYPE >          __asm __volatile( \ >          " " MPLOCKED " " \ >          " cmpxchg %3,%1 ; " \ > - " sete %0 ; " \ >          "# atomic_cmpset_" #TYPE " " \ > - : "=q" (res), /* 0 */ \ > + : "=@cce" (res), /* 0 */ \ >            "+m" (*dst), /* 1 */ \ >            "+a" (expect) /* 2 */ \ >          : "r" (src) /* 3 */ \ > @@ -219,9 +218,8 @@ atomic_fcmpset_##TYPE(volatile u_##TYPE *dst, u_##TYPE >          __asm __volatile( \ >          " " MPLOCKED " " \ >          " cmpxchg %3,%1 ; " \ > - " sete %0 ; " \ >          "# atomic_fcmpset_" #TYPE " " \ > - : "=q" (res), /* 0 */ \ > + : "=@cce" (res), /* 0 */ \ >            "+m" (*dst), /* 1 */ \ >            "+a" (*expect) /* 2 */ \ >          : "r" (src) /* 3 */ \ > @@ -278,9 +276,8 @@ atomic_testandset_int(volatile u_int *p, u_int v) >          __asm __volatile( >          " " MPLOCKED " " >          " btsl %2,%1 ; " > - " setc %0 ; " >          "# atomic_testandset_int" > - : "=q" (res), /* 0 */ > + : "=@ccc" (res), /* 0 */ >            "+m" (*p) /* 1 */ >          : "Ir" (v & 0x1f) /* 2 */ >          : "cc"); > @@ -295,9 +292,8 @@ atomic_testandset_long(volatile u_long *p, u_int v) >          __asm __volatile( >          " " MPLOCKED " " >          " btsq %2,%1 ; " > - " setc %0 ; " >          "# atomic_testandset_long" > - : "=q" (res), /* 0 */ > + : "=@ccc" (res), /* 0 */ >            "+m" (*p) /* 1 */ >          : "Jr" ((u_long)(v & 0x3f)) /* 2 */ >          : "cc"); > @@ -312,9 +308,8 @@ atomic_testandclear_int(volatile u_int *p, u_int v) >          __asm __volatile( >          " " MPLOCKED " " >          " btrl %2,%1 ; " > - " setc %0 ; " >          "# atomic_testandclear_int" > - : "=q" (res), /* 0 */ > + : "=@ccc" (res), /* 0 */ >            "+m" (*p) /* 1 */ >          : "Ir" (v & 0x1f) /* 2 */ >          : "cc"); > @@ -329,9 +324,8 @@ atomic_testandclear_long(volatile u_long *p, u_int v) >          __asm __volatile( >          " " MPLOCKED " " >          " btrq %2,%1 ; " > - " setc %0 ; " >          "# atomic_testandclear_long" > - : "=q" (res), /* 0 */ > + : "=@ccc" (res), /* 0 */ >            "+m" (*p) /* 1 */ >          : "Jr" ((u_long)(v & 0x3f)) /* 2 */ >          : "cc");