Date: Sat, 11 Sep 2010 14:21:03 +0000 (UTC) From: Bruce Cran <brucec@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-7@freebsd.org Subject: svn commit: r212469 - stable/7/sys/dev/sis Message-ID: <201009111421.o8BEL3bc004492@svn.freebsd.org>
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Author: brucec Date: Sat Sep 11 14:21:02 2010 New Revision: 212469 URL: http://svn.freebsd.org/changeset/base/212469 Log: MFC r206909: It's not necessary to reset the chip every time an input overflow event occurs. In addition, the delay when programming the short cable fix should be 100us, not 100ms. PR: kern/64556 Submitted by: Thomas Hurst <tom at hur.st> Approved by: rrs (mentor) Modified: stable/7/sys/dev/sis/if_sis.c Directory Properties: stable/7/sys/ (props changed) stable/7/sys/cddl/contrib/opensolaris/ (props changed) stable/7/sys/contrib/dev/acpica/ (props changed) stable/7/sys/contrib/pf/ (props changed) Modified: stable/7/sys/dev/sis/if_sis.c ============================================================================== --- stable/7/sys/dev/sis/if_sis.c Sat Sep 11 14:18:30 2010 (r212468) +++ stable/7/sys/dev/sis/if_sis.c Sat Sep 11 14:21:02 2010 (r212469) @@ -1480,15 +1480,6 @@ sis_rxeof(struct sis_softc *sc) sc->sis_rx_pdsc = cur_rx; } -static void -sis_rxeoc(struct sis_softc *sc) -{ - - SIS_LOCK_ASSERT(sc); - sis_rxeof(sc); - sis_initl(sc); -} - /* * A frame was downloaded to the chip. It's safe for us to clean up * the list buffers. @@ -1610,7 +1601,7 @@ sis_poll(struct ifnet *ifp, enum poll_cm status = CSR_READ_4(sc, SIS_ISR); if (status & (SIS_ISR_RX_ERR|SIS_ISR_RX_OFLOW)) - sis_rxeoc(sc); + ifp->if_ierrors++; if (status & (SIS_ISR_RX_IDLE)) SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); @@ -1667,7 +1658,7 @@ sis_intr(void *arg) sis_rxeof(sc); if (status & SIS_ISR_RX_OFLOW) - sis_rxeoc(sc); + ifp->if_ierrors++; if (status & (SIS_ISR_RX_IDLE)) SIS_SETBIT(sc, SIS_CSR, SIS_CSR_RX_ENABLE); @@ -2012,7 +2003,7 @@ sis_initl(struct sis_softc *sc) CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001); reg = CSR_READ_4(sc, NS_PHY_DSPCFG) & 0xfff; CSR_WRITE_4(sc, NS_PHY_DSPCFG, reg | 0x1000); - DELAY(100000); + DELAY(100); reg = CSR_READ_4(sc, NS_PHY_TDATA) & 0xff; if ((reg & 0x0080) == 0 || (reg > 0xd8 && reg <= 0xff)) { device_printf(sc->sis_dev,
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