From owner-svn-src-stable-7@FreeBSD.ORG Fri Mar 26 13:01:53 2010 Return-Path: Delivered-To: svn-src-stable-7@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id A94EF1065673; Fri, 26 Mar 2010 13:01:53 +0000 (UTC) (envelope-from jhb@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id 97DD18FC22; Fri, 26 Mar 2010 13:01:53 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.3/8.14.3) with ESMTP id o2QD1rIE052328; Fri, 26 Mar 2010 13:01:53 GMT (envelope-from jhb@svn.freebsd.org) Received: (from jhb@localhost) by svn.freebsd.org (8.14.3/8.14.3/Submit) id o2QD1rR6052325; Fri, 26 Mar 2010 13:01:53 GMT (envelope-from jhb@svn.freebsd.org) Message-Id: <201003261301.o2QD1rR6052325@svn.freebsd.org> From: John Baldwin Date: Fri, 26 Mar 2010 13:01:53 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-7@freebsd.org X-SVN-Group: stable-7 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r205688 - in stable/7/sys: amd64/include i386/include X-BeenThere: svn-src-stable-7@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: SVN commit messages for only the 7-stable src tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 26 Mar 2010 13:01:53 -0000 Author: jhb Date: Fri Mar 26 13:01:53 2010 New Revision: 205688 URL: http://svn.freebsd.org/changeset/base/205688 Log: MFC 205210,205448: Remove unneeded type specifiers from 64-bit constants. The compiler infers their natural type from the constants' values. Modified: stable/7/sys/amd64/include/specialreg.h stable/7/sys/i386/include/specialreg.h Directory Properties: stable/7/sys/ (props changed) stable/7/sys/cddl/contrib/opensolaris/ (props changed) stable/7/sys/contrib/dev/acpica/ (props changed) stable/7/sys/contrib/pf/ (props changed) Modified: stable/7/sys/amd64/include/specialreg.h ============================================================================== --- stable/7/sys/amd64/include/specialreg.h Fri Mar 26 13:01:30 2010 (r205687) +++ stable/7/sys/amd64/include/specialreg.h Fri Mar 26 13:01:53 2010 (r205688) @@ -313,16 +313,16 @@ #define MTRR_N64K 8 /* numbers of fixed-size entries */ #define MTRR_N16K 16 #define MTRR_N4K 64 -#define MTRR_CAP_WC 0x0000000000000400UL -#define MTRR_CAP_FIXED 0x0000000000000100UL -#define MTRR_CAP_VCNT 0x00000000000000ffUL -#define MTRR_DEF_ENABLE 0x0000000000000800UL -#define MTRR_DEF_FIXED_ENABLE 0x0000000000000400UL -#define MTRR_DEF_TYPE 0x00000000000000ffUL -#define MTRR_PHYSBASE_PHYSBASE 0x000ffffffffff000UL -#define MTRR_PHYSBASE_TYPE 0x00000000000000ffUL -#define MTRR_PHYSMASK_PHYSMASK 0x000ffffffffff000UL -#define MTRR_PHYSMASK_VALID 0x0000000000000800UL +#define MTRR_CAP_WC 0x0000000000000400 +#define MTRR_CAP_FIXED 0x0000000000000100 +#define MTRR_CAP_VCNT 0x00000000000000ff +#define MTRR_DEF_ENABLE 0x0000000000000800 +#define MTRR_DEF_FIXED_ENABLE 0x0000000000000400 +#define MTRR_DEF_TYPE 0x00000000000000ff +#define MTRR_PHYSBASE_PHYSBASE 0x000ffffffffff000 +#define MTRR_PHYSBASE_TYPE 0x00000000000000ff +#define MTRR_PHYSMASK_PHYSMASK 0x000ffffffffff000 +#define MTRR_PHYSMASK_VALID 0x0000000000000800 /* Performance Control Register (5x86 only). */ #define PCR0 0x20 @@ -350,22 +350,22 @@ #define MCG_STATUS_RIPV 0x00000001 #define MCG_STATUS_EIPV 0x00000002 #define MCG_STATUS_MCIP 0x00000004 -#define MCG_CTL_ENABLE 0xffffffffffffffffUL -#define MCG_CTL_DISABLE 0x0000000000000000UL +#define MCG_CTL_ENABLE 0xffffffffffffffff +#define MCG_CTL_DISABLE 0x0000000000000000 #define MSR_MC_CTL(x) (MSR_MC0_CTL + (x) * 4) #define MSR_MC_STATUS(x) (MSR_MC0_STATUS + (x) * 4) #define MSR_MC_ADDR(x) (MSR_MC0_ADDR + (x) * 4) #define MSR_MC_MISC(x) (MSR_MC0_MISC + (x) * 4) -#define MC_STATUS_MCA_ERROR 0x000000000000ffffUL -#define MC_STATUS_MODEL_ERROR 0x00000000ffff0000UL -#define MC_STATUS_OTHER_INFO 0x01ffffff00000000UL -#define MC_STATUS_PCC 0x0200000000000000UL -#define MC_STATUS_ADDRV 0x0400000000000000UL -#define MC_STATUS_MISCV 0x0800000000000000UL -#define MC_STATUS_EN 0x1000000000000000UL -#define MC_STATUS_UC 0x2000000000000000UL -#define MC_STATUS_OVER 0x4000000000000000UL -#define MC_STATUS_VAL 0x8000000000000000UL +#define MC_STATUS_MCA_ERROR 0x000000000000ffff +#define MC_STATUS_MODEL_ERROR 0x00000000ffff0000 +#define MC_STATUS_OTHER_INFO 0x01ffffff00000000 +#define MC_STATUS_PCC 0x0200000000000000 +#define MC_STATUS_ADDRV 0x0400000000000000 +#define MC_STATUS_MISCV 0x0800000000000000 +#define MC_STATUS_EN 0x1000000000000000 +#define MC_STATUS_UC 0x2000000000000000 +#define MC_STATUS_OVER 0x4000000000000000 +#define MC_STATUS_VAL 0x8000000000000000 /* * The following four 3-byte registers control the non-cacheable regions. Modified: stable/7/sys/i386/include/specialreg.h ============================================================================== --- stable/7/sys/i386/include/specialreg.h Fri Mar 26 13:01:30 2010 (r205687) +++ stable/7/sys/i386/include/specialreg.h Fri Mar 26 13:01:53 2010 (r205688) @@ -319,16 +319,16 @@ #define MTRR_N64K 8 /* numbers of fixed-size entries */ #define MTRR_N16K 16 #define MTRR_N4K 64 -#define MTRR_CAP_WC 0x0000000000000400ULL -#define MTRR_CAP_FIXED 0x0000000000000100ULL -#define MTRR_CAP_VCNT 0x00000000000000ffULL -#define MTRR_DEF_ENABLE 0x0000000000000800ULL -#define MTRR_DEF_FIXED_ENABLE 0x0000000000000400ULL -#define MTRR_DEF_TYPE 0x00000000000000ffULL -#define MTRR_PHYSBASE_PHYSBASE 0x000ffffffffff000ULL -#define MTRR_PHYSBASE_TYPE 0x00000000000000ffULL -#define MTRR_PHYSMASK_PHYSMASK 0x000ffffffffff000ULL -#define MTRR_PHYSMASK_VALID 0x0000000000000800ULL +#define MTRR_CAP_WC 0x0000000000000400 +#define MTRR_CAP_FIXED 0x0000000000000100 +#define MTRR_CAP_VCNT 0x00000000000000ff +#define MTRR_DEF_ENABLE 0x0000000000000800 +#define MTRR_DEF_FIXED_ENABLE 0x0000000000000400 +#define MTRR_DEF_TYPE 0x00000000000000ff +#define MTRR_PHYSBASE_PHYSBASE 0x000ffffffffff000 +#define MTRR_PHYSBASE_TYPE 0x00000000000000ff +#define MTRR_PHYSMASK_PHYSMASK 0x000ffffffffff000 +#define MTRR_PHYSMASK_VALID 0x0000000000000800 /* * Cyrix configuration registers, accessible as IO ports. @@ -419,22 +419,22 @@ #define MCG_STATUS_RIPV 0x00000001 #define MCG_STATUS_EIPV 0x00000002 #define MCG_STATUS_MCIP 0x00000004 -#define MCG_CTL_ENABLE 0xffffffffffffffffUL -#define MCG_CTL_DISABLE 0x0000000000000000UL +#define MCG_CTL_ENABLE 0xffffffffffffffff +#define MCG_CTL_DISABLE 0x0000000000000000 #define MSR_MC_CTL(x) (MSR_MC0_CTL + (x) * 4) #define MSR_MC_STATUS(x) (MSR_MC0_STATUS + (x) * 4) #define MSR_MC_ADDR(x) (MSR_MC0_ADDR + (x) * 4) #define MSR_MC_MISC(x) (MSR_MC0_MISC + (x) * 4) -#define MC_STATUS_MCA_ERROR 0x000000000000ffffUL -#define MC_STATUS_MODEL_ERROR 0x00000000ffff0000UL -#define MC_STATUS_OTHER_INFO 0x01ffffff00000000UL -#define MC_STATUS_PCC 0x0200000000000000UL -#define MC_STATUS_ADDRV 0x0400000000000000UL -#define MC_STATUS_MISCV 0x0800000000000000UL -#define MC_STATUS_EN 0x1000000000000000UL -#define MC_STATUS_UC 0x2000000000000000UL -#define MC_STATUS_OVER 0x4000000000000000UL -#define MC_STATUS_VAL 0x8000000000000000UL +#define MC_STATUS_MCA_ERROR 0x000000000000ffff +#define MC_STATUS_MODEL_ERROR 0x00000000ffff0000 +#define MC_STATUS_OTHER_INFO 0x01ffffff00000000 +#define MC_STATUS_PCC 0x0200000000000000 +#define MC_STATUS_ADDRV 0x0400000000000000 +#define MC_STATUS_MISCV 0x0800000000000000 +#define MC_STATUS_EN 0x1000000000000000 +#define MC_STATUS_UC 0x2000000000000000 +#define MC_STATUS_OVER 0x4000000000000000 +#define MC_STATUS_VAL 0x8000000000000000 /* * The following four 3-byte registers control the non-cacheable regions.