sK1iZBt6OiRCs3XgHA== ARC-Authentication-Results: i=1; mx1.freebsd.org; none ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1781032654; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=3A7LTvWozkDzAIHlcUCS3Lahl4OXX/29YtnXS4CDaEM=; b=YY3TUfD7Q/gSh35vOSWFn+MgEkEFFJuP8gtiMCddsFRyTykBY5rugcDdclTl41LQObHzae 1pEAps4dQ6IiruQjK1Ez6hV74yIXjZ/P/fqef9GhxjTuVtmwCNn5qKrpkLtmkhi7nQ3/NB YAVNqdmK+gGSiJlsGmrHHWz6iF+1PWfb4jPFwArJ57N8UYpwJQJG2VxjQHsDN/P/bmhvj1 OFIWufFRNnXr4PvVkr46sxsZ+6GXQjlA6bhubnmSiv1E3iFe9NbXAzC0IYzg5U7Hlzp2Fq eAxg95sE3stGpX7fhYy5kXS9Gi8J4sSPVDCy9QhP1Ui53G2d2397dA+coH1azQ== Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) by mxrelay.nyi.freebsd.org (Postfix) with ESMTP id 4gZdvy2kDLzn9W for ; Tue, 09 Jun 2026 19:17:34 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from git (uid 1279) (envelope-from git@FreeBSD.org) id 3cd7a by gitrepo.freebsd.org (DragonFly Mail Agent v0.13+ on gitrepo.freebsd.org); Tue, 09 Jun 2026 19:17:34 +0000 To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-branches@FreeBSD.org Cc: Andrew Turner From: Mark Johnston Subject: git: 9d9d6c6e6081 - stable/15 - arm64: Workaround the following errata List-Id: Commits to the stable branches of the FreeBSD src repository List-Archive: https://lists.freebsd.org/archives/dev-commits-src-branches List-Help: List-Post: List-Subscribe: List-Unsubscribe: X-BeenThere: dev-commits-src-branches@freebsd.org Sender: owner-dev-commits-src-branches@FreeBSD.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: markj X-Git-Repository: src X-Git-Refname: refs/heads/stable/15 X-Git-Reftype: branch X-Git-Commit: 9d9d6c6e608166a9385422c904b585007379f9ce Auto-Submitted: auto-generated Date: Tue, 09 Jun 2026 19:17:34 +0000 Message-Id: <6a2866ce.3cd7a.4e209bcb@gitrepo.freebsd.org> The branch stable/15 has been updated by markj: URL: https://cgit.FreeBSD.org/src/commit/?id=9d9d6c6e608166a9385422c904b585007379f9ce commit 9d9d6c6e608166a9385422c904b585007379f9ce Author: Andrew Turner AuthorDate: 2026-05-28 09:25:30 +0000 Commit: Mark Johnston CommitDate: 2026-06-09 19:15:24 +0000 arm64: Workaround the following errata - ARM C1-Premium erratum 4193780 - ARM C1-Ultra erratum 4193780 - ARM Cortex-A76 erratum 4193800 - ARM Cortex-A76AE erratum 4193801 - ARM Cortex-A77 erratum 4193798 - ARM Cortex-A78 erratum 4193791 - ARM Cortex-A78AE erratum 4193793 - ARM Cortex-A78C erratum 4193794 - ARM Cortex-A710 erratum 4193788 - ARM Cortex-X1 erratum 4193791 - ARM Cortex-X1C erratum 4193792 - ARM Cortex-X2 erratum 4193788 - ARM Cortex-X3 erratum 4193786 - ARM Cortex-X4 erratum 4118414 - ARM Cortex-X925 erratum 4193781 - ARM Neoverse-N1 erratum 4193800 - ARM Neoverse-N2 erratum 4193789 - ARM Neoverse-V1 erratum 4193790 - ARM Neoverse-V2 erratum 4193787 - ARM Neoverse-V3 erratum 4193784 - ARM Neoverse-V3AE erratum 4193784 These are all variants on an erratum where TLBI+DSB instructions on one CPU may incorrectly complete early leading to stores to an updated address using an incorrect translation on another CPU. In all cases the workaround is to add a second TLBI+DSB. Approved by: so Security: FreeBSD-SA-26:31.arm64 Security: CVE-2025-10263 Sponsored by: Arm Ltd --- sys/arm64/arm64/pmap.c | 60 ++++++++++++++++++++++++++++++++++++++++++-------- 1 file changed, 51 insertions(+), 9 deletions(-) diff --git a/sys/arm64/arm64/pmap.c b/sys/arm64/arm64/pmap.c index aa0b0e829f7a..12ab8750c77a 100644 --- a/sys/arm64/arm64/pmap.c +++ b/sys/arm64/arm64/pmap.c @@ -1743,20 +1743,62 @@ static cpu_feat_en pmap_multiple_tlbi_check(const struct cpu_feat *feat __unused, u_int midr) { /* - * Cortex-A55 erratum 2441007 (Cat B rare) + * ARM C1-Premium erratum 4193780 + * ARM C1-Ultra erratum 4193780 + * ARM Cortex-A76 erratum 4193800 + * ARM Cortex-A76AE erratum 4193801 + * ARM Cortex-A77 erratum 4193798 + * ARM Cortex-A78 erratum 4193791 + * ARM Cortex-A78AE erratum 4193793 + * ARM Cortex-A78C erratum 4193794 + * ARM Cortex-A710 erratum 4193788 + * ARM Cortex-X1 erratum 4193791 + * ARM Cortex-X1C erratum 4193792 + * ARM Cortex-X2 erratum 4193788 + * ARM Cortex-X3 erratum 4193786 + * ARM Cortex-X4 erratum 4118414 + * ARM Cortex-X925 erratum 4193781 + * ARM Neoverse-N1 erratum 4193800 + * ARM Neoverse-N2 erratum 4193789 + * ARM Neoverse-V1 erratum 4193790 + * ARM Neoverse-V2 erratum 4193787 + * ARM Neoverse-V3 erratum 4193784 + * ARM Neoverse-V3AE erratum 4193784 * Present in all revisions */ - if (CPU_IMPL(midr) == CPU_IMPL_ARM && - CPU_PART(midr) == CPU_PART_CORTEX_A55) - return (FEAT_DEFAULT_DISABLE); + if (CPU_IMPL(midr) == CPU_IMPL_ARM) { + switch(CPU_PART(midr)) { + case CPU_PART_C1_PREMIUM: + case CPU_PART_C1_ULTRA: + case CPU_PART_CORTEX_A76: + case CPU_PART_CORTEX_A76AE: + case CPU_PART_CORTEX_A77: + case CPU_PART_CORTEX_A78: + case CPU_PART_CORTEX_A78AE: + case CPU_PART_CORTEX_A78C: + case CPU_PART_CORTEX_A710: + case CPU_PART_CORTEX_X1: + case CPU_PART_CORTEX_X1C: + case CPU_PART_CORTEX_X2: + case CPU_PART_CORTEX_X3: + case CPU_PART_CORTEX_X4: + case CPU_PART_CORTEX_X925: + case CPU_PART_NEOVERSE_N1: + case CPU_PART_NEOVERSE_N2: + case CPU_PART_NEOVERSE_V1: + case CPU_PART_NEOVERSE_V2: + case CPU_PART_NEOVERSE_V3: + case CPU_PART_NEOVERSE_V3AE: + return (FEAT_DEFAULT_ENABLE); + } + } /* - * Cortex-A76 erratum 1286807 (Cat B rare) - * Present in r0p0 - r3p0 - * Fixed in r3p1 + * Cortex-A55 erratum 2441007 (Cat B rare) + * Present in all revisions */ - if (midr_check_var_part_range(midr, CPU_IMPL_ARM, CPU_PART_CORTEX_A76, - 0, 0, 3, 0)) + if (CPU_IMPL(midr) == CPU_IMPL_ARM && + CPU_PART(midr) == CPU_PART_CORTEX_A55) return (FEAT_DEFAULT_DISABLE); /*