Date: Thu, 5 May 2011 09:44:35 +0800 From: Adrian Chadd <adrian@freebsd.org> To: freebsd-mips@freebsd.org Subject: RFC: AHB handling for AR71xx/AR913x Message-ID: <BANLkTinSA6tu8p%2BYSGORyaiseP41WebSrQ@mail.gmail.com>
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Hi, Our AR71xx/AR913x SoC support doesn't have an explicit bus nexus for the atheros host bus (AHB), which various things hang off of. These things (the PCI bridge, USB, SPI and ethernet controllers on the AR71xx; the USB, SPI, ethernet, wireless MAC on the AR913x) currently directly connect to nexus0. Now, there's one case with the AR913x where this is a pain, and that's where a DDR flush should be done when IP2 is triggered. There's a similar case on the AR71xx/AR724x but currently the PCI and ethernet controllers do a DDR flush themselves. But there's no convenient place for this to occur for the AR913x wireless MAC (as it connects directly to nexus0). Additionally, according to the AR7100 datasheet, we should be tickling DDR_WB_FLUSH_USB (DDR_BASE+0xA4) after an ISR read. Our USB code doesn't currently handle that. (An aside note, the datasheet says that the DDR registers should be tickled twice, rather than the once we're doing it.) So I propose this: * create an AHB nexus, glued to nexus0; * glue the above devices to it rather than nexus0; * handle AHB errors in this nexus, to aid debugging; * call the relevant DDR flush for USB, PCI, WMAC, etc here That should tidy up all of the bus handling for these SoCs. What do people think? Thanks, Adrian
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