From owner-cvs-src-old@FreeBSD.ORG Thu Aug 5 05:00:25 2010 Return-Path: Delivered-To: cvs-src-old@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 96E8E10656AC for ; Thu, 5 Aug 2010 05:00:03 +0000 (UTC) (envelope-from neel@FreeBSD.org) Received: from repoman.freebsd.org (repoman.freebsd.org [IPv6:2001:4f8:fff6::29]) by mx1.freebsd.org (Postfix) with ESMTP id C3EEA8FC18 for ; Thu, 5 Aug 2010 05:00:03 +0000 (UTC) Received: from repoman.freebsd.org (localhost [127.0.0.1]) by repoman.freebsd.org (8.14.4/8.14.4) with ESMTP id o75503ad023898 for ; Thu, 5 Aug 2010 05:00:03 GMT (envelope-from neel@repoman.freebsd.org) Received: (from svn2cvs@localhost) by repoman.freebsd.org (8.14.4/8.14.4/Submit) id o755031e023897 for cvs-src-old@freebsd.org; Thu, 5 Aug 2010 05:00:03 GMT (envelope-from neel@repoman.freebsd.org) Message-Id: <201008050500.o755031e023897@repoman.freebsd.org> X-Authentication-Warning: repoman.freebsd.org: svn2cvs set sender to neel@repoman.freebsd.org using -f From: Neel Natu Date: Thu, 5 Aug 2010 04:59:54 +0000 (UTC) To: cvs-src-old@freebsd.org X-FreeBSD-CVS-Branch: HEAD Subject: cvs commit: src/sys/mips/mips tick.c src/sys/mips/sibyte sb_machdep.c X-BeenThere: cvs-src-old@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: **OBSOLETE** CVS commit messages for the src tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 Aug 2010 05:00:25 -0000 neel 2010-08-05 04:59:54 UTC FreeBSD src repository Modified files: sys/mips/mips tick.c sys/mips/sibyte sb_machdep.c Log: SVN rev 210854 on 2010-08-05 04:59:54Z by neel Fix a race between clock_intr() and tick_ticker() when updating 'counter_upper' and 'counter_lower_last'. The race exists because interrupts are enabled even though tick_ticker() executes in a critical section. Fix a bug in clock_intr() in how it updates the cached values of 'counter_upper' and 'counter_lower_last'. They are updated only when the COUNT register rolls over. More interestingly it will *never* update the cached values if 'counter_lower_last' happens to be zero. Get rid of superfluous critical section in clock_intr(). There is no reason to do this because clock_intr() executes in hard interrupt context. Switch back to using 'tick_ticker()' as the cpu ticker for Sibyte. Reviewed by: jmallett, mav Revision Changes Path 1.17 +29 -17 src/sys/mips/mips/tick.c 1.13 +0 -2 src/sys/mips/sibyte/sb_machdep.c